JPH0222946A - Transmission data bus with circuit to output 'h' level of null time slot compulsorily - Google Patents

Abstract

PURPOSE:To prevent malfunction from occurring and the GND level from floating by always outputting an 'H' level from a null time slot compulsorily. CONSTITUTION:The title device is the one in which a driver IC11 with gate instead of a pull-up resistor is connected to a transmission data bus 1, and also, the control circuit 10 of the driver IC11 with gate is attached. The null time slot is recognized by the gate control circuit 10, and a gate is opened only during that time, then, the 'H' level is sent to the transmission data bus. In such a way, it is possible to prevent the GND level from floating without using the pull-up resistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time division multiplexing device, and particularly to processing of vacant time slots on a data bus.

[Conventional technology]

Figure 4 is a diagram showing a conventional transmission data bus with a pull-up resistor. In the figure, ... is a transmission data bus, +trt4
h a M7 F repass, (8a), (8b), (
8C) is a terminal worker/1 card person with a transmitting/receiving circuit connected to the transmitting data bus Il+, SuB, SuC, (4a),
(4b), (No. C) is the terminal operator/LP card (8a) (P
+) (8a) has a gated driver area 0sA, sB,
C, (5a), (5b) (io) are terminal cards (8
ACM AT L/X coincidence detection circuit which a), (jb), (8a) have, (6a), (all), r6a) is output by terminal/r card (8a), (8b), (8a) (7) is a pull-up resistor, and (8) is a power supply.

Next, the operation will be explained. Each terminal I/F card (8a
) (8b) (Jlc) indicates that the same address signal as its own address was output to the ACM address path 121.
AcM7); response matching detection circuit (5a), (5b).

(5C) and opens the gate of gated driver air a r4a) rrb) (4c) only in that time slot.

The transmission data (6a) (6b) r6c) are output to the transmission data bus. In other time slots, the gates of the gated driver units 0 (4a), (4b), and (4c) are closed to create a tristate state.

Therefore, all terminal X/F cards (8a) (8b) (8c) connected to the transmission data bus are gates?
When closed (hereinafter this case will be referred to as an empty time slot), the pull-up resistor +71. The transmission data bus +11 was set to the @H level by the power supply (8).

[Problem to be solved by the invention]

In conventional transmission data with a pull-up resistor, the Vc@L I level (,,a
a The waveform of the transmitted data is 5th to transition to the I level.
As shown in the figure, if the constant of the pull-up resistor is large, a malfunction will occur in which the signal is assumed to be "L" at the reception timing (see point (2) in Figure 5).

Conversely, if the pull-up resistor is made smaller, the waveform will look like the dotted line in figure S, and malfunctions will no longer occur (see point ■ in figure 5).
Since the GND level floats and becomes high because it is pulled up at the FLL source, it becomes vulnerable to noise on the GND, and the above-mentioned phenomenon is likely to occur due to temperature changes in the constant of the pull-up resistor. There were some problems.

This invention was made to solve the above-mentioned problems, and the transmission data bus is always @
A I shall be.

[Means to solve the problem]

The transmission data bus with empty time slot lH level forced output circuit according to the present invention connects a gated driver IO to the transmission data bus instead of the conventional pull-up resistor, and adds a control circuit for this gated driver IO. It is.

[Effect]

The transmission data bus with an empty time slot 1H level forced output circuit according to the present invention uses a gate control circuit to select an empty time slot t-&g, opens the gate only for seven periods, and outputs 1H1 to the transmission data bus.

[Implementation row]

Hereinafter, one embodiment-j of the present invention will be explained with reference to the drawings. In FIG. 1, reference numerals 113 to 18c) in FIG. 1 are completely the same as those of the conventional device. In the figure, +101
In the frame gate control circuit, aυ is a driver IC with a gate. FIG. 8 is a block diagram showing a concrete implementation of the gate control circuit [PIJ' in FIG.

11. I! I#: Exactly the same as the conventional one, shown in Figure 1.

+101 and dυ are exactly the same as in FIG.

In the figure, 121 CPO data, Q31 is CPO control data, Q41 is ACM address data,
aω is 1-bit RAM, 111 is an address selector IC 10η is a gated buffer for data bus switching +
1. aS is a buffer analyzer with a gate for data bus switching. 2°σ(1) is CPO address data.

5 free time slots configured as above
The operation of the transmission data bus with af7 bell output circuit will be explained.

First, the address selector a- and data bus switching gated buffers η and +11m are controlled by the OPU control signal al, and the RAM t151 is made accessible to the CPO. Next, the terminals X/Ip connected to the transmission data bus...)' (8a) (8b
) Write the gate 0FIF11+al data to the same RAM address as the address in (8a).

Gate ON control data t- is written in other RAM addresses. After writing is completed.

Address selector a・, gated buffer aη, 01
1 is controlled by the 0PtT control signal decoy, and the ACM
The address data is used as an address to make the RAM accessible. When data is sequentially output to the ACM address bus (21).

The game stored in RAM using that address) 0N
-OFF control data is accessed from the RAM to control the gated driver air aUυ.

In the time slot where the data has been output, that is, the terminal/F card is all in the OFIF state, the gated driver IC is connected to the ONL,
Outputs “H” level.

Conversely, in the time slot where the gate 0IFIF control signal is output, that is, the time slot where any terminal/F card outputs transmission data, the address selector αυ is set to gate OF? do.

Furthermore, on the way, the terminal/y card r8a), (8b), (
When the Jlc) is inserted or removed, the CPO detects this and writes the ON111m signal to the same RAM address as the card address and outputs 1HIt-.

In the above implementation-j, the 1H1 output was simply sent out on the 7th day of the transmission, but as shown in Figure 3 VC, a gated cashier C3υ is connected to the reception data bus ■, and a go operation detection device 〇- is connected to the reception data bus ■. A 1H@level forced output previous monitoring circuit consisting of an alarm generation circuit may be provided.

In this example, the data output to the data bus of the opposing device is received data bus 1! ), but when the time slot is empty, the gated receiver ICwol-gate is turned on and the data is input. A malfunction detection circuit 0- compares whether this is lHl on the data bus, that is, *Ll in the card, and if it is incorrect, the information is sent to the alarm generation circuit and an alarm is generated. Since there is a difference of one bit of the timing clock between the transmission timing and the reception timing, it is necessary to correct this difference by delaying the transmission and reception timing.

〔Effect of the invention〕

As described above, according to the present invention, the 1H level is always forcibly output to an empty time slot, so there is no erroneous previous work, and the GND level does not float, making it resistant to noise.

Furthermore, it has the effect of not being affected by changes in temperature.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a transmission data bus with an empty time slot forced "H" level output circuit according to an example of the present invention;
FIG. 2 is a diagram showing a concrete example of the gate system al [01 road shown in FIG. 1, and FIG. 3 is a diagram showing another embodiment of the present invention [Pl? The figure which shows the gate control circuit shown in FIG. FIG. 4 is a diagram showing a conventional transmission data bus with pull-up resistors, and FIG. 5 is a diagram showing transmission data waveforms in the conventional transmission data bus with pull-up resistors. In the figure, 111 is a transmission data bus, 111+ is a gated driver circuit, 1101 is a gate control circuit, and a
Q is RAM, Qfl is a selector, and Gη and θ♂ are buffers. In addition, in FIG. 1, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Gated driver I connected to the transmission data bus
C. Transmission data with empty slot forced "H" level output circuit, characterized in that this gated driver IC is equipped with a RAM for storing control signal data, and a selector and buffer for accessing data from CPO to this RAM. bus.