JPH02230442A - Cache memory control circuit - Google Patents

Abstract

PURPOSE:To increase the working speed and to attain the change of an address area with a cache memory control circuit by setting an access mode including the direct address area designation into an access mode register. CONSTITUTION:An access mode register 1 outputs a bus access mode signal BAM containing the set one of plural access modes including the address area designation respectively. An access mode decoder 2 decodes the signal BAM and outputs an access control signal AC in the prescribed timing. A comparator 4 compares a tag address TA' stored in a tag memory 3 with a tag address TA inputted by an address signal AD and outputs a hit deciding signal HJ. Then an access control circuit 5 inputs both signals AC and HJ and outputs a cache memory control signal CCNT. In such a constitution, the working speed is increased and the address area can be changed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cache memory control circuit, and particularly to a cache memory control circuit that controls an access mode to a cache memory of an information processing device.

[Conventional technology]

Conventionally, in this type of cache memory control circuit,
Designation of access modes such as cache access mode, cache bypass mode, access cancellation mode 1, etc. according to the address map for the cache memory is performed by specifying the access mode to the cache memory control unit,
This was executed in two stages: specifying control operations within the cache memory control unit.

FIG. 3 is a block diagram showing an example of a conventional cache memory control circuit.

This cache memory control circuit first decodes the bus cycle designation signal BCD and the tag address TA in the bus cycle decoder 6 and outputs the path access designation signal BAD.
The access mode 1 of the cache memory control unit 10 is generated.
-Transmitted to decoder 2B.

Next, in the cache memory control unit 10, the access modes 1 to 2B decode the hash access designation signal BAD and the read/write signal R/W, generate an access control signal AC at a predetermined timing, and send the access control signal AC to the access control circuit 5. introduce.

On the other hand, the comparator circuit 4 compares the tag address TA' stored in the tag memory 3 and the tag address TA input by the address signal AD', generates a judgment signal HJ to the access control circuit 5, and generates a judgment signal HJ to the access control circuit 5. introduce.

The access control circuit 5 is configured to output a cache memory control signal CCNT in accordance with the access control signal AC and the hit/determination signal HJ.

[Invention or problem to be solved]

'' In the conventional dual cache memory control circuit, the pass cycle coder 6 decodes the bus cycle designation signal BCD, and then transmits the output signal to the access motor t' coder 2l1 of the cache memory control unit 10 for decoding. Since the configuration is such that execution is performed in two stages, there is a drawback that the operation of the cache memory control unit 10 is delayed and it becomes difficult to speed up the operation.

Furthermore, since the access mode designation is fixed and the address mapping is fixed, there is a drawback that the address area cannot be expanded or changed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cache memory control circuit that can operate at high speed and change the address area.

[Means to solve the problem]

The cache memory control circuit of the present invention internally sets one of a plurality of access modes 1 to 1 including address area designations, and at least a register to the access mode 1 for outputting a bus access mode I to signal. An access mode 1~tekota which decodes the bus access mode 1 signal and outputs an access control signal at a predetermined timing, and a takua}~res inputted by the tag address and address signal stored in the tag memory. It has a comparison circuit that compares and outputs a hit determination signal, and an access control circuit that inputs the access control signal and the hit 1 to determination signal and outputs a cache memory control signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this embodiment, the address signal AD is first set to the tag address A.
The access mode is composed of T, page address PA, and set 1 to address SA, and one of a plurality of classified access modes including address area designation is input by the page address PA.

To access mode 1, register 1 receives register set signal R.
The access mode input by the page address PA is set internally according to S, and the bus access mode 1/signal BAM is output for each pass cycle.

Access mode decoder 2 has access mode decoder 1'
The signal BAM, pace stress PA, and signals R and /W are input and decoded, and an access control signal AC is output at a predetermined timing.

The tag memory 3 stores tag 1-res (AT'), and sets h i! by set address SA. A selection is made and one taqua address A' is output.

The comparison circuit 4 receives the tag address TA' from the tag memory 3.
and the tag address TA input by the address signal AD, and output the comparison result as a hit-judgment signal HJ.

The access control circuit 5 receives an access control signal A. The configuration is such that the cache memory control signal CCNT is output according to the input of the determination signals C and H1 to HJ to control access to the cache memory.

Therefore, during execution of set I-selection in tag memory 3, access mode 1- is directly set inside access mode 1-resistor 1, and access mode I/resistor 1 outputs hash access mode l-signal BAM. As a result, the speed of operation can be increased. When specifying the map and access mode 1, you can also specify the address area from address 1 to address, so you can change the address area even while the program is running.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

In this embodiment, access modes 1 to 1 are designated by address signals A. The structure is such that input is made using a hash cycle designation signal BCD higher than D, which has the advantage that the address area for the access modes 1 to 1 can be more widely allocated.

〔Effect of the invention〕

As explained below-11, the present invention provides an access mode 1~resistor, and directly sets the access mode 1~ including the access mode 1~l/space area designation therein. Since the decoding operation by the cycle decoder can be eliminated, the delay caused by the hash cycle decoder can be eliminated, which has the effect of speeding up the operation.

In addition, when access mode 1 is specified, the address area can be changed by changing the address area specification, which has the effect of making effective use of the memory space.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing a second embodiment of the present invention, respectively, and FIG. 3 is a block diagram showing an example of a conventional cache memory control circuit. 1, 1A・Access mote register, 2, 2A2B・・
・Tekko to access mode 1, 3...Tag memory, 4...
...Comparison circuit, 5.Access control circuit, 6.Has→no cycle coater, 10-*-A-Tush memory control section.

Claims (1)

[Claims] an access mode register that internally sets one of a plurality of access modes each including address area specification and outputs a bus access mode signal; and an access mode register that decodes at least the bus access mode signal and outputs an access control signal at a predetermined timing. an access mode decoder to output;
a comparison circuit that compares the tag address stored in the tag memory with the tag address input by the address signal and outputs a hit determination signal; and a comparison circuit that inputs the access control signal and the hit determination signal and outputs a cache memory control signal. 1. A cache memory control circuit, comprising: an access control circuit that outputs an output.