JPH0223055B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate control circuit for a gate turn-off thyristor (hereinafter abbreviated as GTO), and particularly relates to a circuit equipped with a pulse transformer that allows on-gate current and off-gate current to flow through the gate control circuit.

Figure 1 shows a conventional GTO gate control circuit.
In this figure, 1 is a GTO, 2 is a pulse transformer, 3 is a DC power supply, 4 is a turn-on transistor, and 5 is a turn-off transistor.
The pulse transformer 2 has a first primary winding 2 ₁₁ , a second primary winding 2 ₁₂ , and a common secondary winding 2 ₂ .

Further, 6 is a transistor, 7 and 8 are resistors, and 9 is a capacitor, which set the conduction time and magnitude of the on-gate current. 10 is a thyristor, 11
are anode ring circuits, which conduct off-gate current. Furthermore, 12 is a wide on-gate circuit that flows a small on-gate current (this is called a wide on-gate current to distinguish it from the previous on-gate current) while the GTO is on.

The operation of this gate control circuit will be explained below with reference to the waveform diagram shown in FIG.

When the transistor 4 is turned on, the transistor 6 is turned on via the first primary winding 2 ₁₁ and the secondary winding 2 ₂ of the pulse transformer 2, and an on-gate current i ₁ flows through the transistor 6 and the resistor 7.
GTO1 turns on. At this time, the waveforms of each part are as shown in Fig. 2, A, B, C, and F. Shown in Figure 1
In the GTO gate control circuit, the magnetization direction of the iron core of the pulse transformer 2 is determined when the transistor 4 is turned on and an on-gate current flows through the first primary winding ₂₁₁ , and when the transistor 5 is turned on and the second The off-gate current flows in the primary winding 2 ₁₂ in the opposite direction to prevent saturation of the iron core. Therefore, the on-time _t1 of the transistor 4 changes the magnetization state of the iron core of the pulse transformer 2 from the magnetization state of the transistor 4 when the transistor 5 is turned on and an off-gate current flows through the second primary winding ₂₁₂ . The time is set to be enough to reset the transistor 6 to the reverse magnetization state when the transistor 6 is turned on and an on-gate current flows through the first primary winding ₂₁₁ .
The on-time _t2 is set to a time that allows the minimum necessary on-gate current to flow. transistor 6
The on-time t ₂ of is determined by the time constant of the circuit of resistor 8 and capacitor 9.

While GTO1 is on, wide on-gate circuit 12
passes a small wide on-gate current i ₂ as shown in FIG. During this time, both the transistor 6 and the thyristor 10 are off, and the wide on-gate current flows through the secondary winding 2 of the pulse transformer 2.
It is designed not to flow to ₂ .

Next, when the transistor 5 is turned on, a voltage opposite to that previously induced is induced in the secondary winding ₂₂ of the pulse transformer 2, the thyristor 10 is turned on, an off-gate current _i3 flows, and the GTO 1 is turned off. At this time, the waveforms of each part are as shown in Fig. 2 (D), (E), and (F).
The on time _t3 of transistor 5 is also pulse transformer 2.
The magnetization state of the iron core is changed from the magnetization state when transistor 4 is turned on and an on-gate current flows through the first primary winding ₂₁₁ to the magnetization state when transistor 5 is turned on and an on-gate current flows through the first primary winding 211.
The time is set to return the magnetization state to the opposite direction when the off-gate current flows through the primary winding 2 ₁₂ of the primary winding 2 12 , so-called setting time.
Since the number of turns of the secondary winding 2 ₁₁ and the second primary winding 2 ₁₂ are the same, t ₁ =t ₃ .

FIG. 3 shows changes in off-gate current i ₃ , anode current i ₄ , and gate voltage v when the GTO is turned off. The impedance between the cathode and the gate is small during the storage period from when the off-gate current _i3 starts flowing until it turns off, but
When the GTO turns off, it has a withstand voltage of about 20V. When a voltage higher than the above breakdown voltage is applied from the gate control circuit between the cathode and gate of the GTO, after the GTO is turned off, a relatively large current called an avalanche current flows as shown by the broken line in the figure. When this avalanche current flows, the power consumption of the gate control circuit increases, and the gate loss of the GTO itself increases.
The GTO's gate control circuit is configured so that no avalanche current flows.

In other words, in a normal gate control circuit, the cathode
The gate voltage is set to be equal to or lower than the withstand voltage. For example, when the voltage of the DC power supply 3 is 100V, the turns ratio of the second primary winding 2 ₁₂ and the secondary winding 2 ₂ is approximately 5:1, and the induced voltage of the secondary winding 2 ₂ is The generation of avalanche current is prevented by ensuring that the voltage does not exceed the withstand voltage of 20V.

In this way, in conventional gate control circuits, in order to prevent avalanche current from flowing, the output voltage of the pulse transformer at turn-off is regulated to, for example, about 20V, and the output voltage of the pulse transformer is regulated to about 20V.
Since the number of turns of the next winding is the same, the output voltage of the pulse transformer at turn-on is also 20V.
There is a drawback that the rise of the on-gate current cannot be made steep. The time required for the on-gate current to rise is determined by gate turn-off thyristor 1 and resistor 7.
Let L be the inductance included in the flow path, and R be the resistance value of the resistor 7, then L/R. Therefore, in order to make the rise steep, it is necessary to increase R. However, the resistance value R of the resistor 7 is determined by the output voltage of the pulse transformer 2 and the value of the on-gate current flowing through the GTO 1, so if the output voltage of the pulse transformer 2 is low, the resistance value R of the resistor 7 cannot be increased. . Therefore, if the output voltage of the pulse transformer 2 is low, the rise of the on-gate current cannot be made steep, and the turn-on of the GTO 1 is delayed.

In addition, in pulse width modulation type inverters using GTO, it is strongly desired to reduce the GTO minimum on time and minimum off time as much as possible from the perspective of improving inverter performance. In the case of a conventional gate control circuit, the minimum on-time is regulated by the on-time _t1 of the turn-on transistor 4, and cannot be made shorter than this. Conventionally, the on-time _t1 of the transistor 4 is set to a time sufficient to reset the pulse transformer, as described above, and the on-gate current flow time _t2 required for turn-on is set to 2.
~3 times longer. In this way, conventional gate control circuits reduce the time required to turn on the GTO.
Although t ₂ is much smaller than the GTO's minimum on-time (approximately t ₁ ), the disadvantage is that the minimum on-time cannot be made smaller.

The object of the present invention is to eliminate the drawbacks of the above-mentioned prior art, to enable quick turn-on of the GTO, and to
The object of the present invention is to provide a GTO gate control circuit that can reduce the minimum on-time of the GTO.

To achieve this objective, the present invention provides two primary windings for turn-on and turn-off and a common secondary winding.
one pulse transformer with a second winding
In the gate control circuit of the GTO, the turns ratio between the second primary winding and the secondary winding for turn-off is set to such an extent that no avalanche current flows, as in the conventional case.
The number of turns of the first primary winding for turn-on is set to the second
The number of turns of the primary winding is smaller than that of the primary winding, and the output voltage of the pulse transformer at turn-on is increased.

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIG.

In Figure 4, 1 is GTO, 3 is DC power supply,
4 is a turn-on transistor, 5 is a turn-off transistor, 10 is a thyristor through which an off-gate current flows, 11 is an anode firing circuit thereof, and 12 is a wide on-gate circuit, which are the same as those of the conventional circuit. This embodiment is different from the conventional one in that the number of turns of the first primary winding 13 ₁₁ of the pulse transformer 13 is smaller than the number of turns of the second primary winding 13 ₁₂ , and that the circuit that conducts the on-gate current is composed of a diode 14 and a resistor 15 having a higher resistance value than the conventional one.

The numbers of turns of the second primary winding 13 ₁₂ and the secondary winding 13 ₁₂ of the pulse transformer 13 are the same as in the conventional case, and for example, when the voltage of the power supply 3 is 100V, the turns ratio is 5:1. This prevents the generation of avalanche current. On the other hand, the first
The number of turns of the primary winding 13 ₁₁ is made smaller than the number of turns of the second primary winding 13 ₁₂ determined as described above. For example, if the number of turns of the first primary winding 13 ₁₁ is reduced to half of the number of turns 13 ₁₂ of the second primary winding,
If the turns ratio between the primary winding 13 ₁₂ and the secondary winding 13 ₂ is 5:1, the turns ratio between the first primary winding 13 ₁₁ and the secondary winding 13 ₂ is 2.5:1. . By doing this, the output voltage of the pulse transformer at turn-on is doubled compared to the conventional one, and the resistance value of the resistor 15 can be doubled compared to the conventional one, so a steeply rising on-gate current can be obtained, and the GTO1 Turn-on can be made faster. Also, the voltage of the DC power supply 3 is V, the reset time of the pulse transformer 13 is t,
The number of turns of the first primary winding 13 ₁₁ of the pulse transformer 13 is n, the cross-sectional area of the iron core is S, and the magnetic flux density of the iron core is B.
Then, the reset time t is given by the following equation.

t=n・S・B/V As is clear from this equation, pulse transformer 1
Since the reset time t of No. 3 is proportional to the number of turns of the first primary winding ₁₃₁₁ , if this number of turns is halved, the reset time will be halved, and therefore the turn-on transistor 4 The on-time of the GTO can also be reduced to half of the conventional one, and the minimum on-time of the GTO can be significantly shortened. Furthermore, if the on time of transistor 4 is reduced by half,
Since this is close to the minimum necessary conduction time of the on-gate current, the transistor 6, resistor 8, and capacitor 9 in FIG.
can be replaced by , which simplifies the circuit.

FIG. 5 is a waveform diagram of each part of the circuit of the above embodiment. The on-time _t3 of the turn-off transistor 5 is the same as the conventional one, but the on-time _t1 of the turn-on transistor ₄ is half of t3, and the rise of the on-gate current _i1 is steeper. It shows that you are getting used to it.

In the above embodiment, mainly the first primary winding 13
Although the case where the turns ratio between ₁₁ and the second primary winding 13 _and 12 is 1:2 has been described, this turns ratio is not limited to 1:2; It is within the scope of the present invention that the number of turns of the second primary winding be less than the number of turns of the second primary winding. However, this turns ratio is preferably equal to or almost equal to the ratio of the minimum required on-gate current conduction time (time corresponding to t ₂ in Figure 2) and off-gate current conduction time t ₃ . It is better to set the values close to each other. This is because the transistor, resistor, and capacitor for setting the conduction time of the on-gate current can be omitted and replaced with one diode. Of course, since the main purpose of the present invention is not to omit the above-mentioned transistors, etc., there is no problem in using these parts in the same manner as in the past.

As explained above, according to the present invention, the output voltage of the pulse transformer at turn-on increases and the rise of the on-gate current becomes steep, so that the GTO
Since the turn-on of the GTO becomes faster and the time for applying voltage to the first primary winding of the pulse transformer during turn-on becomes shorter, there is an advantage that the minimum on-time of the GTO can be shortened.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an example of a conventional GTO gate control circuit, Figure 2 A to F are waveform diagrams of various parts in the same circuit, Figure 3 is a waveform diagram of various parts when the GTO is turned off, and Figure 4 5 is a circuit diagram showing one embodiment of a gate control circuit for a GTO according to the present invention, and FIGS. 5A to 5C are waveform diagrams of various parts in the same circuit. 1...GTO (gate turn-off thyristor),
3...DC power supply, 4...Turn-on transistor, 5...Turn-off transistor, 10...
Thyristor for off-gate current flow, 13...Pulse transformer, 13 ₁₁ ...First primary winding, 13 ₁₂
...Second primary winding, 13 ₂ ...Secondary winding, 14
...On-gate current carrying diode, 15...
resistance.

Claims (1)

[Scope of Claims] 1. A pulse transformer that passes an on-gate current that turns on the gate turn-off thyristor and an off-gate current that turns it off; a second primary winding through which the off-gate current flows; and a secondary winding connected to the gate/cathode circuit of the gate turn-off thyristor and common to the on-gate current and off-gate current. and a common DC power supply connected to the first primary winding and the second primary winding to supply the on-gate current and the off-gate current to each of these primary windings; a first switching element connected to the first primary winding to turn on/off the on-gate current; a second switching element connected to the second primary winding to turn on/off the off-gate current; and a switching element control means for controlling on/off of each switching element, wherein the number of turns of the first primary winding is smaller than the number of turns of the second primary winding, and the switching element control means controls the switching element. A gate control circuit for a gate turn-off thyristor, characterized in that the on-time of the first switching element is set to be shorter than the on-time of the second switching element. 2. In claim 1, the ratio of the number of turns of the first primary winding to the number of turns of the second primary winding is determined by the on-time of the first switching element and the second switching element. A gate control circuit for a gate turn-off thyristor, characterized in that the value is set according to the on-time ratio of the element.