JPH02230588A - Optical disk controller - Google Patents

Abstract

PURPOSE:To accelerate the processing time of a microprocessor by providing a means to compare track information with sector information by a processing range holding means and a present processing address recognizing means, and a means to permit the transfer of data based on the coincidence of comparison. CONSTITUTION:The processing range holding means 3-5 to hold a processing range instructed by a host device and the present processing address recognizing means 1 and 2 to recognize a position where a head is positioned at present are provided, and the track information and the sector information from the processing range holding means 3-5 and the present processing address recognizing means 1 and 2 are compared at comparison means 6-8, and the transfer of the data is permitted based on the coincidence of the comparison. Thereby, since the processing range supplied from the host device is processed independently, the ID recognition time of the microprocessor can be shortened and accelerated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an optical disc control device.

[Conventional technology]

Conventionally, writing and reading processing for multiple sectors by an optical disk control device has been controlled by a microprocessor for each sector.

FIG. 3 generally shows the format of an optical disc medium. The medium is made up of a number of blocks 200, which consists of track 2Q1.

Furthermore, the track 201 is composed of a sector 203, and the sector 203 is composed of an ID section 205 and a data section 206.

If the optical disk control device receives a command to read from the start sector 204 to the track last sector 207, it will read the ID section and search for it, and if it finds it, it will read and store that data section, and if it reads the next ID section and it is correct, it will read that data. memorize the part.

Thereafter, processing was performed by reading up to the last sector 207 in the same manner.

[Problem to be solved by the invention]

The conventional multi-sector write and read process described above is
Since the microprocessor controls each sector,
Since it is necessary to secure processing time for the microprocessor between sectors, there is a drawback that high speed cannot be achieved.

[Means to solve the problem]

The optical disc control device of the present invention includes processing range holding means for holding a processing range commanded from a host device, current processing address recognition means for recognizing a position where a head currently exists, the processing range holding means and the current processing The apparatus includes a comparison means for comparing track information and sector information from the address recognition means, and a transfer permission means for permitting data transfer based on a comparison by the comparison means.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows a schematic block diagram of the optical disc control device of this embodiment. Host device 51 and optical disk device 5
6, the line passing through the upper part of the figure is the write data line, the line passing through the center is the read data line, and the lower part is the main control line.

First, starting from the main control line, control signals from the host device 51 or control signals to the second-order device 51 are sent via the host interface circuit 66. Similarly, a device interface circuit 63 is provided for the optical disc device.

The host interface circuit 66 and the device interface circuit 63 are connected to the MPU bus 67 and the address bus 68.
These are mainly controlled by a microprocessor (MPU) 65.

The MPU 65 receives information from the RAM 65 via the bus, and sends information to the buffer control circuit 57 and error correction/detection (E
CC) circuit 60 and ID detection circuit 59.

Write data sent from the host device 51 is sent via a write data transfer circuit 52 to a write data buffer 53 controlled by the buffer control circuit 57, and then sent to an optical disk device 56 via an encoding circuit 54 and a modulation circuit 55. recorded.

The read data is demodulated by a demodulation circuit 58, and the demodulated data is sent to an ID detection circuit 59 and an ECC circuit 60. Next, after an error is detected in the FCC circuit 60, the data is sent to the read data buffer 61 controlled by the buffer control circuit 57, and sent to the host device via the read data transfer circuit 62.

On the other hand, the demodulated data input to the ID detection circuit 59 is UD
When the information is detected, the ID detection circuit 59 sends a control signal to the next FCC circuit 60 and buffer control circuit 59 based on the information. A timing signal 69 output from the device interface circuit 63 is used to detect ID information.

The present invention resides in this ID detection circuit. To explain the outline,
The MPU 65 recognizes the range of data processing based on track and sector information in response to a command from the host device 51, and instructs the ID detection circuit 59. The ID detection circuit 59 obtains the above information, performs the search, buffer writing, and buffer reading independently, and sends a completion report to the MPU 65.

Next, the ID detection circuit 59, which is a feature of the present invention, will be explained with reference to FIG.

The circuit shown in FIG. 1 particularly shows only the portion of the present invention of the ID detection circuit 59, and other portions are intentionally not shown. Therefore, the input/output signals in FIG. 1 do not completely correspond to the input/output signals of the ID detection circuit 59 in FIG. 2.

First, the input/output signals shown in FIG. 1 will be explained. In the figure, a signal input from the left side is processed and output from the right side.

In the input signal, ID bus 101 is a signal read from an optical disk. The MPU bus 102 is a signal sent from the MPU 65 to specify the range of sectors to be processed. The reset 165 is a signal for initializing all processing, and is also generated on the MPU bus 67. Other input signals are for timing and are present in the timing signal 69.

61 Only the range-indicating output signals are shown.

The start signal 140 is activated when the beginning of the range is found, and the sector end signal 155 is activated when the end of the range is found.
Each is output.

Next, each block will be explained.

ID} Rack register 1 holds the number of the track currently being read by the head. ID sector register 2 similarly holds the number of the sector currently being read by the head. Track address counter 3 holds the track number to be read.

In other words, when searching, the starting track number of the processing range is retained, and if the processing range spans multiple tracks,
Raise it before moving on to the next track.

The start sector register 4 holds the starting sector of the processing range. The track last sector register 5 holds the number of the last sector of the track held in the track address counter 3. That is, when the processing range extends over a plurality of tracks, it is necessary to know the final sector in order to increment the track address counter 3. The selector counter 13 holds the number of remaining sectors to be processed. The number of sectors held here is decreased every time 21 sectors are processed, and when it reaches 4, a sector end signal 155 is output.

The track comparator 6 compares the track number currently being read by the head with the processing track number. The start sector comparator 7 similarly compares sectors. The track last sector comparator 8 is used to confirm the last sector of a track when the processing range extends to a plurality of tracks.

The shift register 18 generates a timing signal from a sector pulse 151 that is output when the head passes a certain position in a sector, and a sector pulse shift clock 152 that is output at a constant cycle. The generated timing signal is further processed by inverter 19 and AND20.

A logic circuit consisting of AND9, AND23, and OR10 outputs a signal to the start flip-flop 11 when the start of the processing range is found and when the processing range is being tracked and a start signal is being output. do. The start flip-flop 11 returns to its initial value when the AND 21 and OR 22 logic circuit outputs a sector end signal indicating the end of the processing range or when the reset 165 is input. The track last sector flip-flop 12 updates the track address counter 3 when it recognizes the last sector of the track in the processing range. This flip-flop 12 returns to its initial value only when a reset 165 is input. Sector end flip-flop 16 is OR 14
It is reported by the inverter 15 that the sector power counter 13 has become zero, and a sector end signal 155 is output, indicating the end of the processing range. This flip flop 16
is also initialized by reset 165.

AND17 is within the processing range and when passing through a sector, adds 1 to the sector counter.

Next, the operation of this embodiment will be specifically explained with reference to the time chart of FIG. In FIG. 4, it is assumed that the processing range is 9T, the start is the track number Tas, the sector number Sas}, the final sector number of the rack Ta is Ls, and the number of sectors to be processed is Sn, starting from the upper numerical value 51.

FIG. 4(A) shows a processing range holding process.

The above information is sent in parallel on the MPU bus 102 at any time. When Ta is on the MPU bus 102, the track address count load 132 is output, and at the rising edge of the load, the track address counter output becomes Ta. Similarly, the processing range is held in each output.

FIG. 4(B) shows a process of recognizing the track and sector that the head is currently passing through, especially the process of recognizing the beginning of the processing range. The head is passing through the ID portion of the sector. At the timing when the ID bus 101 indicates Ta, the ID
}Rack light 130 is output. At the rising edge of the ID rack write 130, the ID rack register 103 is updated to Ta, and the track address counter output 104
Since the track match signal becomes equal to the level of 1, the track match signal becomes 1101.

On the other hand, when the ID bus 10] indicates Sa, the ID sector write 131 is output, and the D sector register output 105 is updated to Sa, and this value becomes the stat sector register output 1.
．． Since it is the same value as 0 6, a sector match is also recognized,
Since the track and sector match, a star l/hold signal 139 is output.

FIG. 4(c) shows a process for reducing the number of sectors to be processed within the processing range. When the sector pulse 151 is input, a delay signal is generated at a period of sector pulse shift 1 clock 152. Sector pulse shift 1) 1. 5 7 is inverted by inverter 19 and sector pulse shift b inverted 1
60, and this inversion 160 and sector pulse shift l-
When both a 1 5 6 are at the 1 level, the signal is output. Especially at this time, since it is within the processing range, the sector counter 1/down 162 is output, and at this rising edge, the sector power counter output 108 is counted down by 1. Ru.

FIG. 4(D) shows the process when looking at the last sector of 1 rack in the processing range. When the ID sector register output 105 becomes Ls, it is the same value as 1・Lack class 1・Sector register output 107, so 1・Lack class 1・
The sector match signal 137 becomes a high level. In this state, when the sector pulse shift dl59, which is a delay signal of the sector pulse 151, goes high, the track last sector signal 141 goes to the no level, and 1 is added to the 1/rack address power counter output 104.

FIG. 4(E) shows the end process of the processing range.

The process up to the sector power down in FIG. 4(C) is the same as described above, but this time, since the sector counter output 108 becomes zero, the output of the OR 14 becomes a low level.

This causes the sector power counter zero inversion 154 to
Become a bell. In this state, sector pulse shift l.c ].
5 The rising edge of 8 is the sector end flip-flop 16.
When the sector end signal]55 is inputted to
- The reset 164 is output and the star l signal 140 goes low, reporting that the processing range has ended.

The following is an explanation of this embodiment. Although this embodiment can be implemented with a simple configuration, there is another method in which the value of the C start sector register 4 is also incremented by 1 as in the case of the rack address power counter 3. Since this system constantly manages ID racks and sectors, reliability tends to be poor, but the structure tends to be complicated.

〔Effect of the invention〕

As explained below, the present invention processes the processing range given by the host device independently from the microprocessor, thereby reducing the time required for the microprocessor to recognize the process, which was previously necessary. The gap between the ID section and the data section can also be reduced, which has the effect of increasing the speed and density of the optical disk device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a schematic block diagram of an optical disk control device, and FIG. 3 shows the configuration of processing blocks on an optical disk medium. FIG. 3 is a timing diagram showing the control operation of the transfer of the data. 1...ID} Rack register, 2...
ID selector register, 3...1 Rack address power counter, 4...Start selector register, Death...Track last sector register, 6
...Track comparator, 7...Start sector comparator, 8...Track last sector comparator, 9...And, 1
0...OR, 11...Start flip-flop, 12...1 Rack last sector flip-flop, 13...Sector counter, 14... ...OR,]5...Inverter, 16...Sector end flip-flop,]
7...and, 18...shift register, 19...inverter, 20...and, 21...and, 22... ...or, 23...and. Agent Patent Attorney Shinichi Uchihara 141

Claims (1)

[Scope of Claim] In an optical disc control device that performs writing/reading processing based on ID information preformatted on the optical disc medium, which is an optical disc medium configured by further aggregating tracks each composed of a plurality of selectors. , processing range holding means for holding a processing range commanded from a host device; current processing address recognition means for recognizing the position where the head currently exists; and track information and information from the processing range holding means and current processing address recognition means. 1. An optical disc processing device comprising: comparison means for comparing sector information; and transfer permission means for permitting data transfer based on a comparison of the comparison means.