JPH0223058B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a digital system that synchronizes the timing of data transmission between each communication device in a half-duplex communication system in which data transmission between a plurality of communication devices is performed via a single transmission line. This invention relates to a phase control synchronizer.

In order to realize data transmission between a plurality of communication devices, a communication system using, for example, a half-duplex communication method is configured. In digital communication systems using this half-duplex communication method, data transmission is performed with the timing of the clock signal on the transmitter side and the clock signal on the receiver side accurately synchronized in order to ensure reliable sampling of the transmitted data. It is essential to do so. In half-duplex communication systems that do not have a dedicated transmission line for clock signals, the receiver extracts the transmitting clock signal that is transmitted along with the data from the transmitter, and the extracted transmitting clock signal is used as the receiver's clock signal. By synchronizing with the clock signal, the timing deviation of the clock signal in each communication device is corrected.

FIG. 1 shows one communication device 11 in a conventional half-duplex communication system, and a plurality of communication devices similar to this are connected to a transmission line 12.

The communication device 11 has a digital phase locked circuit 13 (DPLL) as a terminal.
This circuit 13 includes an oscillator 14, and the oscillation pulse signal from the oscillator 14 is passed through a pulse remover 15 and a pulse train adder 16, and then counted by a counter 17. A clock signal is generated when a number, for example 32, is counted. This clock signal is then supplied as a synchronous clock signal to a digital transmitter 18 and a digital receiver 19 connected to the transmission line 12.

Further, a pulse adder 20 is connected to the pulse string adder 16, and supplies future pulses as additional pulses. The adder 16 adds the additional pulses generated from the pulse adder 20 to the pulse train from the pulse remover 15, and the counter 17 counts the added pulses.

Here, the synchronized clock signal of the received digital data transmitted via the transmission line 12 is extracted by a clock extractor 21, and the synchronized clock signal of the received digital data transmitted via the transmission line 12 is extracted by a clock extractor 21,
The phase of the clock signal from the counter 17 is compared with the clock signal from the counter 17, and the pulse remover 15 removes the pulse signal from the oscillator 14 as appropriate, or the pulse adder 20 adds pulses as needed to separate the clock generated from the counter 17 and the received signal. This is to match the synchronization relationship with the synchronous clock.

That is, the phase comparator 22 is the clock extractor 2.
For example, from the clock signal from 1 and the counter 17,
It compares the phase difference with the transmitting/receiving clock signal generated in units of 32 pulses, and if the clock signal from counter 17 is ahead in phase, the pulse remover issues a pulse removal command to counter 15. However, if the phase of the clock signal from the counter 17 is delayed, a pulse addition command is sent to the pulse adder 20.

Here, the oscillator 14 generates two systems of pulse signals with a phase difference of 180 degrees, and these two systems of pulse signals are supplied to a pulse remover 15 and a pulse adder 20, respectively. The pulse remover 15 is
The pulse signal from the oscillator 14 is normally passed through as is, and when the pulse removal command is issued, one pulse of the pulse signal is removed. Further, the pulse adder 20 does not normally pass the pulse signal from the oscillator 14, but allows one pulse of the pulse signal to pass when the pulse addition command is issued.

In the above-mentioned digital communication system, there is no need to extract a clock signal for each bit cycle of transmitted data, so an encoding method such as AMI (Alternate Mark Inversion) that meets the requirements of the transmission line 12 is adopted. There is.

However, when the terminal of the communication device 11 is configured using the digital phase synchronization circuit 13 as described above, when the communication device 11 is in the transmitting state, the clock extractor 21 is operated in the same manner as when the communication device 11 is in the receiving state. A transmitting clock is extracted from the transmission line 12, that is, the digital transmitter 18, and the phase comparator 22 compares the phase of this transmitting clock with the transmitting/receiving clock from the counter 17.

The two clocks whose phases are compared in this way are
Originally, the same clock is generated from the counter 17, but the transmission clock has a phase delay due to passing through circuit elements such as the digital transmitter 18 and the clock extractor 21.

Therefore, in the phase comparator 22, the phases of the transmitting clock from the digital transmitter 18 and the transmitting/receiving clock from the counter 17 do not match semi-permanently, and the digital phase synchronization circuit 13 adjusts the phase no matter how many times. In this case, the two clocks cannot be synchronized. By the way, when a signal is sent by the transmitting clock made in such a way that the transmitting/receiving clock from the counter 17 is always continuously subjected to phase correction of one pulse, other communication devices that receive this signal (the same model as the terminal that sent data), the phase must always be corrected by one pulse, and if this is combined with a new phase shift that would otherwise have to be compared and corrected, the digital phase synchronization circuit 13 exceeds its limit, and the clock signals of the transmitter and receiver of the transmitter in the receiving state become unsynchronized.

This invention was made to solve the above-mentioned problems, and enables reliable synchronization without causing a phase shift between the transmitting clock and the receiving clock of a communication device in the transmitting state. An object of the present invention is to provide a digital phase control synchronizer.

That is, the digital phase control synchronizer according to the present invention includes a transmitting clock generator and a receiving clock generator provided in a terminal connected to a transmission line, and each of the clock generators generates a clock signal at a different timing. , which allows stable phase synchronization control during transmission.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows its configuration, and shows one of a plurality of communication devices 11 connected to the transmission line 12, similar to the case shown in FIG. The terminal of this communication device 11 is equipped with a clock signal generation circuit consisting of an oscillator 14, a pulse remover 15, a pulse adder 20, a pulse train adder 16, and a counter 17. Extract the signal and use the phase comparator 22
The pulse remover 15 and adder 20 are controlled in the same manner as described above.

The counter 17 repeatedly counts the addition pulse train from the pulse train adder 16 in units of, for example, 32 pulses, and the binary data composed of bit information from the counter 17 is sent to the transmitting clock generator 30 and the receiving clock. Generator 31
supply to. The transmitting clock generator 30 and the receiving clock generator 31 decode the count pattern based on the binary data from the counter 17 and generate clock pulses at appropriate timings, respectively. Specifically, a clock pulse is generated at the timing of the specified count value of the counter 17. This clock pulse for transmission is supplied to the digital transmitter 18, and the clock pulse for reception is supplied to the digital receiver 19 and the phase comparator 2.
Supply to 2.

In other words, in the device configured in this way,
The clock generation timings of the transmitting clock generator 30 and the receiving clock generator 31 are set to the amount of phase shift that the transmitting clock would receive if it passed through the clock extractor 21 via the digital transmitter 18. I'll do what I do.

That is, when the communication device 11 is in the transmitting state, the phases of the transmitting clock and the receiving clock compared by the phase comparator 22 always match.
When the communication device 11 is in the receiving state, the receiving clock signal from the receiving clock generator 31 and the clock extracted from the transmission line 12 are phase-corrected and synchronized by the same operation as shown in FIG. be done.

FIG. 3 shows an example of the configuration of the counter 17 and the transmission clock generator 30. The counter 17 is supplied with an addition pulse train from the pulse train adder 16. As this counter 17, for example, a 4-bit binary counter ranging from a ₀ (lowest) to a ₃ (highest) is used.
The bit count data is provided to a clock generator 30. This clock generator 30 has g=
It is composed of a gate logic circuit ₃₂ that generates a pulse output g of 1.a ₃ + _{2.a 3 + a} 1.a _2.3 . That is, this gate logic circuit 32 decodes the count data from the counter 17 as an array of logic gates, and generates clock pulses at timings based on the design of the gate logic circuit 32.

That is, from the pulse train adder 16 to the counter 17
For example, if the pulse train supplied to the clock generator 30 is set to a pulse train with a period T from t=0 and a pulse width 1/4T, the clock generator 30 outputs a pulse train with a period T from t=6T and a pulse width 1/4T from t=6T.
A clock pulse with a pulse width of 8T is now generated.

In other words, since the period and pulse width of the clock pulse from the clock generator 30 can be set arbitrarily by the design values of the gate logic circuit 32, the transmitting clock generator 30 can generate clock pulses at desired timing. . Although not particularly shown, the reception clock generator 31 is similarly constructed.

Therefore, according to the above-described device, when the communication device 11 is in the transmitting state, the transmitting clock is connected to the digital transmitter 18 and the clock extractor 21.
By giving in advance the phase shift received by
During transmission, the phases of the clocks compared by the phase comparator 22 match, so that a stable synchronizing clock pulse can always be obtained without unnecessary phase correction.

In the above embodiment, as shown in FIG. 2, a receiving clock generator 31 is connected to one input terminal of the phase comparator 22 to compare the phase with the clock signal from the clock extractor 21. However, the binary counters _a0 to a3 shown in FIG. ₃ are directly connected to the phase comparator 2.
2 for phase comparison.

FIG. 4 shows the configuration of the phase comparator 22 in this case, and the count data from the counter 17 is sent to two logic circuits 34a and 34b of the phase determination section 33.
supply to. One logic circuit 34a is a counter 1
The logic circuit 34b turns on when the bit pattern of the count data from 7 indicates the first half of the clock cycle, and the other logic circuit 34b turns on when the bit pattern indicates the second half of the clock cycle.
The output signals from these two logic circuits 34a and 34b are inputted to terminals D of the phase advance register 35a and the phase lag register 35b, respectively. If synchronization is achieved, the bit pattern will indicate exactly half the clock period. Do nothing at this time.

These two registers 35a and 35b latch the signal input to terminal D of the phase advance register 35a if the bit pattern is in the first half of the clock cycle at the moment when the clock signal is supplied from the clock extractor 21. When the bit pattern is in the second half of the clock cycle, the signal input to terminal D of the delay register 35b is latched and output from terminal Q. These two registers 35a and 35b The output signal is supplied to the pulse removal command generation section 36a and the pulse addition command generation section 36b.

The pulse removal command generation section 36a issues a pulse removal command to the pulse remover 15 when the signal from the phase advance register 35a is supplied, and the pulse addition command generation section 36b receives the signal from the phase delay register 35b. When supplied, a pulse addition command is sent to the pulse adder 20, and at the same time as each command is sent, each corresponding register 35
A reset signal is supplied to the clear terminals CLR of clocks a and 35b in preparation for the next clock signal from the clock extractor 21.

As described above, according to the present invention, a transmitting clock generator and a receiving clock generator are provided in a terminal connected to a transmission line, and each of the clock generators generates a clock signal at a different timing. Since phase synchronization control can be performed stably during transmission, unnecessary phase correction of the clock signal of the communication device during transmission can be prevented, and a clock signal with stable timing can always be obtained. .

Therefore, even if a communication device that has been in the transmitting state for a long time changes to the receiving state, the phase of the clock signal between the transmitting side and the receiving side can be adjusted because a stable receiving clock signal is always obtained. It can be synchronized instantly and reliably. This makes it possible to speed up data transmission between each communication device, and to sufficiently improve reliability in the half-duplex communication system.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram illustrating a conventional digital phase synchronization circuit, and FIG. 2 is a configuration diagram illustrating a digital phase control synchronization device according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating an example of the circuit of the counter and clock generator in the above embodiment, and FIG. 4 is a diagram illustrating another embodiment of the present invention, and is a block diagram showing the phase comparator taken out. . 12... Transmission line, 14... Oscillator, 15... Pulse remover, 16... Pulse train adder, 17... Counter, 18... Digital transmitter, 19... Digital receiver, 20... Pulse adder, 21... Clock extractor, 22 ...phase comparator, 30...transmission clock generator, 31...reception clock generator.

Claims (1)

[Claims] 1. Digital phase control synchronization that synchronizes the timing of data transmission between each communication device in a half-duplex communication system in which data transmission between multiple communication devices is performed via a single transmission line. The device includes an oscillator, a counter that counts the oscillation pulse train from this oscillator, a reception clock generator that generates a reception clock signal according to the number of pulses counted by this counter, and a synchronous clock signal that is extracted from the transmission line. a phase comparator that compares the phase difference between the synchronous clock signal extracted by the clock extractor and the reception clock signal generated by the reception clock generator; a pulse adder that adds the number of pulses counted to the previous counter when the reception clock signal is ahead in phase than the synchronous clock signal; and a pulse adder that adds the number of pulses counted to the previous counter; a pulse remover that removes the number of pulses counted by the previous counter when it is compared with a phase lag, and a transmitting clock that gives the first reception clock signal a phase difference according to the number of pulses counted by the previous counter. The transmitting clock generator includes a transmitting clock generator that generates a signal, and a transmitter that transmits the transmitting clock signal generated by the transmitting clock generator to a transmission line, and the transmitting clock generator generates a transmitting clock signal. A digital phase control synchronization device characterized in that the phase difference to be provided is set in accordance with the phase shift received from the time of generation of the transmission clock signal to the time of extraction of the synchronous clock signal by the clock extractor.