JPH02230594A - Refresh control circuit - Google Patents

Abstract

PURPOSE:To prevent a refresh operation from missing by storing a refresh address once by attaching a first-in first-out register, and executing the refresh operation after acquiring the right of using a bus. CONSTITUTION:When a timing pulse to instruct to perform the refresh operation at every constant interval by a timer circuit 1 is generated, a refresh counter 2 is counted up, and simultaneously, data before counting up is written on the first-in first-out register(FIFO register 3). Then, an output ready signal 13 goes to a high level, and requests the right of using the bus to a memory use right arbitrator 4. When the right of using the bus is acquired, the FIFO register 3 reads out the refresh address, and executes the refresh operation by outputting the content of the address to an address bus 11. Thereby, it is possible to prevent information from being missed due to the loss of the refresh address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is a control device for a personal computer or the like that uses a dynamic random access memory, in which the dynamic random access memory is used as a RAS ONL.
The present invention relates to a refresh control circuit for providing a refresh address for Y refresh.

[Conventional technology]

Dynamic random access memory (DRAM) is
Since information is stored using internal charges, the charges lost due to discharge are compensated for by a recharging operation called refresh to prevent information from being lost. For this refresh operation, a RAS ONLY refresh method is generally used in which the DRAM matrix is accessed column by column. At this time, a timer accesses the DRAM at regular intervals, and the contents of the refresh counter, which indicates the address to be refreshed, conflict with the timing of memory access by the central processing unit (CPU) or input/output device (I./O device). The DRAM is being accessed to prevent

[Problem to be solved by the invention]

As mentioned in 2 above, in the past, it was necessary to adjust the memory access rights of other CPUs, I/O devices, etc. that were trying to access the memory, and then secure the right to use the refresh control circuit or memory to perform refresh. It won't happen. in this case,
The refresh control circuit consists of a simple timer and a counter, so if the memory usage right is not secured and a refresh operation is not executed within the timing interval driven by the timer, this counter will start counting based on the output of the next timer. This has the disadvantage that the address to be refreshed is lost, leading to information loss. For this reason, it is generally necessary to set the refresh control circuit's memory usage right at a high priority to ensure that it can acquire the memory usage right, and also to
Alternatively, the I/O device cannot continuously occupy memory for a long time that exceeds the refresh interval.

[Means to solve the problem]

The refresh control circuit of the present invention is a refresh circuit that is driven at regular intervals to obtain the right to use the bus and refresh a dynamic access memory.
By writing to the O register and storing it, even if the right to use the lotus is not secured within a certain interval at which refresh is required, the refresh address is not lost, thereby allowing dynamic random access. It is designed to retain the stored contents of the memory and eliminate momentary hustlenecks.

That is, the refresh control circuit of the present invention includes a timer circuit that outputs a timing pulse instructing to perform a refresh operation at fixed time intervals, and a timer circuit that inputs the timing pulse and counts up, and at the same time fastens data before counting up. 1~Inquer Stow I-
The refresh counter to be written to the register and the data are input to request the bus usage right from the memory usage right arbiter, and when the memory usage right arbiter acquires the bus usage right, the refresh address is read and the address is assigned. It is provided with the above-mentioned first 1, first 1, first 1, first and second registers for outputting.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, a timer circuit 1 generates and outputs timing pulses instructing to perform a refresh operation at regular intervals (about 16 μs for one i). The refresh counter 2 shifts the count 1 hair by this timing pulse, and at the same time transfers the data before the count up to the first-in-first 1 register (
Write to FIFO register 3). FIFO data
When writing to register 3, output ready signal (OR
Signal〉13 becomes high level and memory use right arbitrator 4
request bus usage rights. When the bus usage right is acquired, the memory usage right arbiter 4 selects the S of the FIFO register 3.
A signal is returned to the O terminal and the address to be refreshed (refresh address) is read.

The content of the read address is output to address buses 11-11- to execute a refresh operation.

〔Effect of the invention〕

As explained above, the refresh control circuit of the present invention adds a FIFO register to perform a refresh operation that always needs to be performed at regular intervals.
By temporarily storing the response, when the CPU or I/O device uses the memory for a long time after the predetermined interval for refresh, the refresh operation that could not be executed before can be performed without having the right to use the bus. This has the effect of preventing the refresh operation from being omitted, and the memory usage rate is low or momentarily exceeds the predetermined interval of the refresh operation. Another advantage is that I/O devices that continue to use memory for a long time can also be connected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Timer counter, 2... Refresh address counter, 3... FIF○ register, 4... Memory use right arbitrator, 5... Bus driver.

Claims (1)

[Claims] a timer circuit that outputs a timing pulse instructing to perform a refresh operation at regular time intervals, and a refresh counter that inputs the timing pulse, counts up, and at the same time writes data before counting up to a first-in-first-out register. , the first-in-first-out inputting the data and requesting the memory use right arbiter for the bus use right, and when the memory use right arbiter acquires the bus use right, reading the refresh address and outputting it to the address bus; A refresh control circuit comprising a register.