JPH02230718A - Aligning mark and manufacture thereof - Google Patents

Aligning mark and manufacture thereof

Info

Publication number
JPH02230718A
JPH02230718A JP1049905A JP4990589A JPH02230718A JP H02230718 A JPH02230718 A JP H02230718A JP 1049905 A JP1049905 A JP 1049905A JP 4990589 A JP4990589 A JP 4990589A JP H02230718 A JPH02230718 A JP H02230718A
Authority
JP
Japan
Prior art keywords
silicon
oxide film
etching
mask
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1049905A
Other languages
Japanese (ja)
Inventor
Shigeyuki Sugito
杉戸 重行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1049905A priority Critical patent/JPH02230718A/en
Publication of JPH02230718A publication Critical patent/JPH02230718A/en
Pending legal-status Critical Current

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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Electron Beam Exposure (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To obtain a secondary electron signal having the sufficient strength for mark detection by using a silicon groove comprising a silicon step part wherein the end part of a selected oxide film that is formed on a silicon substrate as a profile as an aligning mark. CONSTITUTION:A mask comprising a silicon nitride film 4 is used, and a silicon oxide film 5 and a silicon substrate 1 undergo dry etching, and a silicon groove is formed. Then, an element isolating silicon oxide film (selected oxide film) 6 is formed by thermal oxidation. The silicon nitride film 4 and the silicon oxide film 5 as a buffer are removed by wet type etching. Then, an element region 7 is covered with photoresist. With the selected oxide film 6 as an etching mask, the silicon substrate 1 is directly etched by reactive ion etching, and an aligning mark 8 is formed. When said aligning mark 8 is used, the strength of the secondary electron signal that is five times or more the strength when the step of an ordinary selected oxide film is used as a mask can be obtained.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は電子線直接描画により半導体装置を製造する際
に必要な目合わけマークおよびその作製方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to alignment marks necessary for manufacturing semiconductor devices by electron beam direct writing and a method for manufacturing the same.

[従来の技術1 従来、電子線直接描画用の目合わせマークは、シリコン
半導体装置の場合には、第3図に示す如く、シリコン基
板1上に直接段差を設けて溝2を形成する方法や、第4
図に示す如く、シリコンの選択酸化によって形成ざれた
選択酸化11g3間に生ずる段差をそのまま利用する方
法か用いられていた。
[Prior art 1] Conventionally, in the case of silicon semiconductor devices, alignment marks for electron beam direct writing have been made by directly providing a step on a silicon substrate 1 to form a groove 2, as shown in FIG. , 4th
As shown in the figure, a method was used in which the step difference between the selective oxidation layers 11g3 formed by selective oxidation of silicon was utilized as is.

[発明が解決しようとする課題] しかしながら、シリコン段差は半導体装置製造工程の最
初に形成ざれるため、プロセスが進み、選択酸化膜形成
や膜堆積などが繰り返されるにつれて段差が低減し、目
合わせのための段差端部からの2次電子信号が得られに
くくなる。また選択酸化膜の段差を利用する場合も、半
導体装置の高集積化と微細化が進むにつれ、素子分離用
の選択酸化領域を狭めるため、選択酸化膜の段差を抑え
る工夫がなされたり、ざらには選択酸化膜厚も簿膜化の
傾向にあるため、シリコン段差と同様に段差喘部からの
2次電子信号が得られにくくなってきている。
[Problems to be Solved by the Invention] However, since silicon steps are not formed at the beginning of the semiconductor device manufacturing process, as the process progresses and selective oxide film formation and film deposition are repeated, the steps decrease and alignment becomes difficult. Therefore, it becomes difficult to obtain a secondary electron signal from the step end. In addition, when using the step difference in the selective oxide film, as the integration and miniaturization of semiconductor devices progress, in order to narrow the selective oxidation region for element isolation, measures are being taken to suppress the step difference in the selective oxide film, and Since the selective oxide film thickness also tends to decrease, it is becoming difficult to obtain secondary electron signals from the step part, similar to the silicon step.

本発明は、以上述べたような従来の事情に対処してなさ
れたもので、半導体装置の高集積化や微細化に適した電
子線直接描画用の目合わせマークおよびその作製方法を
提供することを目的とする。
The present invention has been made in response to the above-mentioned conventional circumstances, and it is an object of the present invention to provide an alignment mark for electron beam direct writing, which is suitable for high integration and miniaturization of semiconductor devices, and a method for manufacturing the same. With the goal.

[課題を解決するための手段] 本発明は、シリコン基板上に形成ざれた選択酸化膜の端
部を輪郭とするシリコン段差部よりなるシリコン溝で構
成されてなることを特徴とする目合わけマークであり、
またその作製方法は、シリコン基板上の所定位置に選択
酸化膜を形成すると共に、該選択酸化膜領域以外の領域
にシリコンを露呈させる工程と、露呈したシリコン而の
うち目合わせマーク部以外の領域を保護膜で覆う工程と
、前記保護膜および前記選択酸化膜をマスクとしてシリ
コンをエッチングし、シリコン溝を形成させる工程とを
備えてなることを特徴とする。
[Means for Solving the Problems] The present invention provides an alignment method characterized in that it is constituted by a silicon groove consisting of a silicon stepped portion whose contour is the edge of a selective oxide film formed on a silicon substrate. mark,
The manufacturing method includes the steps of forming a selective oxide film at a predetermined position on a silicon substrate, exposing silicon in areas other than the selective oxide film area, and exposing silicon in areas other than alignment marks. The method is characterized by comprising a step of covering with a protective film, and a step of etching silicon using the protective film and the selective oxide film as a mask to form a silicon groove.

また本発明の方法における第1の工程には、選択酸化膜
を形成する前段階としての、窒化シリコン膜によるマス
クを形成する段階と、形成ざれたマスクを用いて選択酸
化部にシリコン溝を形成する段階を含んでいてもよい。
Further, the first step in the method of the present invention includes a step of forming a mask with a silicon nitride film as a step before forming a selective oxide film, and a step of forming a silicon groove in the selective oxidation part using the formed mask. It may also include a step of.

[作用] シリコン基板とシリコン酸化膜の異方性エッチングの際
のエッチング速度の差は十分に大きくすることかでき、
選択酸化後の酸化膜をエッチングマスクとすれば、酸化
膜の端部を輪郭とするシリコンの段差が形成できる。ま
た、その深さはエッチングにより自由に調整できるので
、マーク検出に十分な強度の2次電子信号を得ることか
できる。
[Function] The difference in etching speed during anisotropic etching of the silicon substrate and silicon oxide film can be made sufficiently large.
If the oxide film after selective oxidation is used as an etching mask, it is possible to form a silicon step whose outline is the edge of the oxide film. Further, since the depth can be freely adjusted by etching, it is possible to obtain a secondary electron signal with sufficient intensity for mark detection.

[実施例] 次に、本発明について図面を参照して説明する。[Example] Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を工程順に示す目合わせマー
ク部の断面図である。
FIG. 1 is a sectional view of an alignment mark portion showing an embodiment of the present invention in the order of steps.

その方法は、まず第1図(a)の如く、選択酸化前のシ
リコン窒化膜4よりなるマスクを形成した後、これをマ
スクにシリコン酸化膜5およびシリコン基板1をドライ
エッチングしてシリコン溝を形成する。その際のシリコ
ン窒化摸4の下の緩衝用のシリコン酸化膜5の厚さは0
.05l!In、シリコン窒化膜4の厚さは0.17μ
s、シリコン溝のエッチング深さは0.22珈であった
The method is to first form a mask made of silicon nitride film 4 before selective oxidation, as shown in FIG. Form. At that time, the thickness of the buffering silicon oxide film 5 under the silicon nitride film 4 is 0.
.. 05l! The thickness of the In, silicon nitride film 4 is 0.17μ
s, the etching depth of the silicon groove was 0.22 mm.

次いで、第1図(b)に示す如く、熱酸化により素子分
離用のシリコン酸化膜(選択酸化膜)6を0.5s1形
成し、シリコン窒化膜4と緩衝用のシリコン酸化膜5を
湿式エッチングにより除去する。
Next, as shown in FIG. 1(b), a silicon oxide film (selective oxide film) 6 for element isolation is formed for 0.5s1 by thermal oxidation, and the silicon nitride film 4 and the silicon oxide film 5 for buffering are wet etched. Remove by.

次にフォトリソグラフィーにより素子領域7をフォトレ
ジストでカバーし、目合わせマーク部を露出させた後、
塩素ガスを用いた反応性イオンエッチングにより選択酸
化膜6をエッチングマスクとして直接シリコン基板1を
エッチングする。エッチング後にフtトレジストを酸素
プラズマで剥離することにより、第1図(C)に示す如
く目合わせマーク8が形成ざれる。その際のシリコン溝
エッチング深さは0.5庫とした。
Next, the element region 7 is covered with photoresist by photolithography, and the alignment mark portion is exposed.
Silicon substrate 1 is directly etched by reactive ion etching using chlorine gas using selective oxide film 6 as an etching mask. After etching, the foot resist is removed using oxygen plasma to form alignment marks 8 as shown in FIG. 1(C). The silicon groove etching depth at that time was set to 0.5 depth.

第1図(C)の構造の目合わせマークを用いた場合、第
1図(b)の通常の選択酸化膜の段差をマクとして用い
た場合の5倍以上の2次電子信号強度を得ることができ
た。
When using the alignment mark with the structure shown in Figure 1(C), it is possible to obtain a secondary electron signal intensity that is 5 times or more than when using the step of the normal selective oxide film as shown in Figure 1(b) as a mark. was completed.

第2図は本発明の仙の実施例を工程順に示す目合わせマ
ーク部の断面図である。
FIG. 2 is a cross-sectional view of an alignment mark portion showing an embodiment of the present invention in the order of steps.

その方法は、まず選択酸化前の第1のシリコン窒化膜マ
スク4aを形成した後、ざらにCVD法により第2のシ
リコン窒化膜4bを全面に堆積し、フォトリソグラフィ
ー工程により選択酸化膜を形成する部分のレジストを開
孔し、ドライエッチングによりシリコン窒化膜4bを除
去した後、ざらに弓続きドライエッチングによりシリコ
ン基板1に溝を形成する(第2 (a))。その際のシ
リコン窒化膜の下の緩衝用のシリコン酸化膜5の厚さは
0.05μm、第1のシリコン窒化膜4aの厚さはOi
7ptn、第2のシリコン窒化膜4bの厚さは0.03
41a、シリコン溝のエッチング深さは0.22 /J
であった。
The method is to first form a first silicon nitride film mask 4a before selective oxidation, then roughly deposit a second silicon nitride film 4b over the entire surface by CVD, and then form a selective oxide film by a photolithography process. After opening a hole in the resist portion and removing the silicon nitride film 4b by dry etching, a groove is formed in the silicon substrate 1 by rough and continuous dry etching (2nd (a)). At this time, the thickness of the silicon oxide film 5 for buffering under the silicon nitride film is 0.05 μm, and the thickness of the first silicon nitride film 4a is Oi
7ptn, the thickness of the second silicon nitride film 4b is 0.03
41a, the etching depth of the silicon groove is 0.22/J
Met.

しかる後、第2図(b)に示す如く、熱酸化により素子
分離用のシリコン酸化膜(選択酸化膜)6を0.5廟形
成し、シリコン窒化膜4a, 4bと緩衝用のシリコン
酸化膜5を湿式エッチングにより除去する。
Thereafter, as shown in FIG. 2(b), a silicon oxide film (selective oxide film) 6 for element isolation is formed with a thickness of 0.5 cm by thermal oxidation, and silicon nitride films 4a and 4b and a silicon oxide film for buffering are formed. 5 is removed by wet etching.

次にフォトリソグラフィーにより素子領域7をフォトレ
ジストでカバーし、目合わせマーク部を露出させた後、
塩素ガスを用いた反応性イオンエッチングにより選択酸
化膜6をエッチングマスクとして直接シリコン基板1を
エッチングする。エッチング後に゜フォトレジストを酸
素プラズマで剥離することにより、第2図(C)に示す
如く目合わせマーク8か形成ざれる。その際のシリコン
溝エッチング深さは0,5珈とした。
Next, the element region 7 is covered with photoresist by photolithography, and the alignment mark portion is exposed.
Silicon substrate 1 is directly etched by reactive ion etching using chlorine gas using selective oxide film 6 as an etching mask. After etching, the photoresist is removed using oxygen plasma to form alignment marks 8 as shown in FIG. 2(C). The silicon groove etching depth at this time was set to 0.5 mm.

第2図(C)の構造の目合わせマークを用いた場合、第
2図(b)の通常の選択酸化膜の段差をマークとして用
いた場合の10倍以上の2次電子信号強度を得ることか
できた。
When using the alignment mark with the structure shown in FIG. 2(C), it is possible to obtain a secondary electron signal intensity that is 10 times higher than when using the normal selective oxide film step shown in FIG. 2(b) as a mark. I was able to do it.

[発明の効果] 以上説明したように、本発明によれば電子線直接描画の
マーク検出に必要な2次電子信号を十分な強度で得るこ
とのできる目合わせマークおよびその作製方法が提供ざ
れる。
[Effects of the Invention] As explained above, according to the present invention, there is provided an alignment mark and a method for producing the same that can obtain a secondary electron signal with sufficient intensity necessary for mark detection by electron beam direct writing. .

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本発明の一実施例を工程順に示す
目合わせマーク部の断面図、第3図および第4図は従来
技術による目合わせマーク部の断面図である。 ]・・・シリコン基仮    2・・・溝3,6・・・
選択酸化膜 4. 4a, 4b・・・シリコン窒化膜5・・・シリ
コン酸化111J    7・・・素子領域8・・・目
合わせマーク
FIGS. 1 and 2 are sectional views of an alignment mark portion showing an embodiment of the present invention in the order of steps, and FIGS. 3 and 4 are sectional views of an alignment mark portion according to the prior art. ]...Silicon base temporary 2...Groove 3, 6...
Selective oxide film 4. 4a, 4b...Silicon nitride film 5...Silicon oxide 111J 7...Element region 8...Alignment mark

Claims (2)

【特許請求の範囲】[Claims] (1)シリコン基板上に形成された選択酸化膜の端部を
輪郭とするシリコン段差部よりなるシリコン溝で構成さ
れてなることを特徴とする目合わせマーク。
(1) An alignment mark comprising a silicon groove formed by a silicon step portion whose outline is the edge of a selective oxide film formed on a silicon substrate.
(2)シリコン基板上の所定位置に選択酸化膜を形成す
ると共に、該選択酸化膜領域以外の領域にシリコンを露
呈させる工程と、露呈したシリコン面のうち目合わせマ
ーク部以外の領域を保護膜で覆う工程と、前記保護膜お
よび前記選択酸化膜をマスクとしてシリコンをエッチン
グし、シリコン溝を形成させる工程とを備えてなること
を特徴とする目合わせマークの作製方法。
(2) Forming a selective oxide film at a predetermined position on the silicon substrate, exposing silicon in areas other than the selective oxide film area, and covering the exposed silicon surface with a protective film in areas other than the alignment marks. 1. A method for producing an alignment mark, comprising the steps of: covering with a silicone film and etching silicon using the protective film and the selective oxide film as a mask to form a silicon groove.
JP1049905A 1989-03-03 1989-03-03 Aligning mark and manufacture thereof Pending JPH02230718A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1049905A JPH02230718A (en) 1989-03-03 1989-03-03 Aligning mark and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1049905A JPH02230718A (en) 1989-03-03 1989-03-03 Aligning mark and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH02230718A true JPH02230718A (en) 1990-09-13

Family

ID=12844025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1049905A Pending JPH02230718A (en) 1989-03-03 1989-03-03 Aligning mark and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH02230718A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121836A (en) * 1982-12-28 1984-07-14 Fujitsu Ltd Formation of positioning mark
JPS62229944A (en) * 1986-03-31 1987-10-08 Toshiba Corp Method of forming positioning mark

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121836A (en) * 1982-12-28 1984-07-14 Fujitsu Ltd Formation of positioning mark
JPS62229944A (en) * 1986-03-31 1987-10-08 Toshiba Corp Method of forming positioning mark

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