JPS6189633A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To conduct mask-matching in high precision even after the completion of a prescribed process, by etching a substrate to form an alignment key prior to the execution of a semiconductor device manufacturing process or the prescribed process. CONSTITUTION:A substrate 1 is etched by a prescribed method, and thereby an alignment key portion 6 having such difference in levels as enables mask- matching is formed. Next, after a first SiO2 film and a first Si3M4 film are formed, these films and the substrate 1 are etched, with a prescribed photoresist pattern used as a mask, to form a first SiO2 pattern 2, a first Si3N4 pattern 3 and a groove 4 for a separating region. Thereafter a second SiO2 film 7 is formed on the side and bottom surfaces of the groove 4 by a thermal oxidation method or the like, and then a second Si3N4 film 8 is formed on the whole surface by a vacuum CVD method or the like. The second Si3N4 film 8 is etched subsequently so as to remove same only from the bottom surface of the groove 4. Afterward, a third SiO2 film 9 is formed in the groove 4 so as to form an insulating separating region, and then the Si3N4 film and the first SiO2 film pattern 2 are removed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an alignment key used for mask alignment. .

Conventional configuration and its problems Traditionally, mask alignment was performed by a person using a microscope to align the alignment keys formed on the semiconductor substrate and the alignment keys formed on the mask. # As the density of conductor integrated circuits increases, automatic mask alignment methods have become mainstream to improve mask alignment accuracy. However, as integrated circuit processes become more complex, changes in the substrate surface increase and alignment accuracy becomes more difficult. deteriorates.

For example, when forming a separation region using the LOCO5 method, which does not cause bird's beak, an alignment key is formed at the same time.
Figure 1 shows the case in which this occurs.

First, a first 5in2 film and a first Si 3 film are formed on a semiconductor substrate 1.
After forming the N4 film, the first S, IO, 2 film, first Si, N4 film, and semiconductor substrate 1 are etched using a predetermined photoresist pattern (not shown) as a mask. A 5102 pattern 2, a first Si pattern, an N4 pattern 3, and a trench 4 in the isolation region are formed.

At this time, the active region portion 6 and the alignment portion 6 are usually formed at the same time (see FIG. 1).

Next, a second 5.
After forming the 102 film 7, a second Si 2 and N 4 film 8 is formed on the entire surface by low pressure qVD method or the like (FIG. 2B).

・Next, the second Si is etched using an anisotropic dry etching method etc.
, the N4 film 8 is etched, and only the lower surface of the groove 4 is etched with Si,
Remove N4 (FIG. 1C) - After that, a third Si0 layer is formed in the groove 4 by, for example, high pressure oxidation method.
．． , tla9 and an isolation region, Si3N
4 film and the first SiO2 pattern 2 (first
Figure D).

By using such a method, the isolation region can be formed without reducing the size of the active region portion 5 due to bird's beak, but a recess 10 is formed at the edge of the isolation region.

Further, these four portions similarly occur at the edge portions of the separation regions that are in contact with the alignment key portion 6.

FIG. 2 shows an example of automatic mask alignment using alignment keys formed by such a method.

This is performed by automatically aligning the alignment key portion 6 formed on the semiconductor substrate 1 and the alignment key region 11 on the mask using visible light, ultraviolet light, or the like.

However, if there is a recess 10 at the edge of the separation region, it will cause a malfunction when automatically performing alignment, and if alignment accuracy is low or alignment cannot be performed, a problem will occur. Problems arise such as a decrease in t, or a decrease in the rate of fine movement of the device.

Also, this phenomenon occurs as described above, in addition to the case where there are some extra lines around the alignment key part 60 of the insect, the steps of the alignment key prayer 6 formed on the substrate; This also occurs when - is very small, or when the alignment portion 6 of the substrate is not a straight line but has irregularities.

OBJECTS OF THE INVENTION The present invention provides a method for manufacturing a semiconductor device that enables E1 mask alignment even after a predetermined process is completed by etching a semiconductor substrate and forming an alignment key before a predetermined process. It is intended to.

Structure of the Invention The present invention forms an alignment key by etching a semiconductor substrate before performing a semiconductor device manufacturing process or a predetermined process, and automatically performs alignment after the predetermined process is almost unaffected by the process. A first embodiment of the semiconductor device manufacturing method of the present invention is shown in FIGS. 3A to 3D, which is a semiconductor device manufacturing method that can be performed with high precision.

First, the semiconductor substrate 1 is etched by a predetermined method to form an alignment portion 6 having a step (for example, about 0.1 to 0.3 μm) that allows mask alignment (see FIG. 3).

Next, after forming a first 515Na film and a first 515Na film, a first 5io2+ film, a first Si3N4 film, and a first 515Na film were formed using a predetermined photoresist pattern (not shown) as a mask.
Etching the semiconductor substrate 1 to form a first 8102 pattern 2
, the first 513N4 pattern 3 and the groove 4 of the isolation region are formed.

Thereafter, a second SiO2 film 7 is formed on the side and bottom surfaces of the trench 4 by thermal oxidation or the like, and then a second 5i5N4 film 8 is formed over the entire surface by low pressure CVD or the like (FIG. 3B).

Next, the second Si,
The N4 film 8 is etched to remove the Si and N4 films only from the bottom surface of the trench 4 (FIG. 3C).

After that, a third 5102 film 9 is formed in the trench 4 (.') by high-pressure oxidation, etc., and an insulating isolation region is formed.
Remove the 5N4 film and the first 5102 hatern 2 (
Figure 3D).

Next, a second implementation 1f11<1 is shown in FIGS. 4A-D.

First, the semiconductor substrate 1 is etched by a predetermined method to form an alignment key portion 6 having a step (for example, about 0.1 to 0.3 μm) that allows mask alignment (see FIG. 4).

Next, a first 8102 film and a first Si 5 film were applied to the conductor substrate 1.
After forming the N4 film, using a predetermined photoresist pattern (not shown) as a mask, the first 8102 film and the first
S i sN 4Hs'+tH,, the semiconductor substrate 1 is etched, the first 5102 Bakun 2, the first Si
3N 4 grooves/(not shown) to form grooves 4 in the separation region.

Next, a second layer is formed on the bottom surface and bottom surface of the groove 4 by thermal oxidation.
After forming 5102 film 7 of
A Si film 12 is formed. Next, when a photoresist film 13 is applied by spin code removal, the photoresist film thickness in the groove 4 portion is thicker than in other regions. At this time, the 60-level difference in the alignment part is small, so it is hardly formed thick (41st JB).

Next, the photoresist film 13 is etched by an anisotropic dry etching method or the like until all of the photoresist film except the groove 4 portion is removed, leaving a photoresist pattern 13' only in the groove 4 portion.

Next, using this photoresist film 13' as a mask, the polySi film 12 is etched by dry etching or the like, leaving the polySi film 12' only in the groove 4 (FIG. 4C).

Next, the photoresist film 13' is removed, the Po1ySi film 12' is oxidized, a third 5102 film 14 is formed, and an insulating isolation region is formed. The putter 72 is removed (FIG. 4D).

By performing the above method, no recesses or the like will be generated around the alignment key even if the insulation separation process is performed.

An example of automatically performing mask alignment after the insulation separation process is completed using the alignment keys formed by the method described above will be described.

The alignment key area 6 formed on the semiconductor substrate and the alignment key area 11 on the mask are automatically aligned using visible light, ultraviolet light, or the like, and are perfectly aligned.

At this time, since there are no extra lines or irregularities around the alignment key area 6 formed on the semiconductor substrate that could cause malfunction, alignment with high accuracy, speed, and loop can be achieved as in the normal case. can.

As described above, by using the method of the present invention, only a part of the alignment key can be formed independently, so the alignment key 0 width and depth can be adjusted arbitrarily so that the aspect ratio of the alignment key is the best regardless of the process. In addition, since the semiconductor substrate is etched, the alignment, alignment, and key shapes hardly change during normal processes, so high-precision mask alignment can be performed regardless of the process.

Note that although both the first and second embodiments have been described using an insulation separation process that tends to cause major problems especially when performing automatic alignment, the method of the present invention is not limited to insulation separation processes. Even in normal processes, it can be used in processes where the step difference in a part of the alignment key becomes very small, a process where the pattern width of the alignment key changes drastically, a process where a capacitor is formed by forming a groove, etc. .

Furthermore, although this embodiment describes only the case where the semiconductor substrate is directly etched, it may also be formed by a method in which a thin 5i02 film or the like is formed and then both the formed four films and the semiconductor substrate are etched. This is advantageous in terms of contamination compared to the case where a photoresist is applied directly onto a semiconductor substrate to create an alignment key pattern.

Although this embodiment describes only the case where a portion of one alignment key is formed, a plurality of alignment keys may be formed at the same time and used for mask alignment at different levels.

Furthermore, in this example, the Si, N4 films and the first 5i02 pattern are removed after the isolation region is formed, but depending on the process, either may not be removed or only the Si and H4 films may be removed before the mask alignment step is performed. Also good.

Further, the method of the present invention can be used not only for conventional light exposure methods but also for alignment methods that require an alignment key, such as in the case of X-ray exposure and EB exposure.

In addition, it is especially necessary when it is necessary to leave the photoresist in the entire self-aligned line by utilizing the step difference in the groove, as in the second implementation row. It is easy to adjust the level difference so that no resist remains on a part of the alignment key.

Effects of the Invention As mentioned above, by using the uninvented method, mask alignment can be performed with high accuracy and high throughput without the decrease in mask alignment accuracy and throughput caused by alignment keys, and its industrial value is It's thick.

[Brief explanation of drawings]

Figures 1A to 1D are cross-sectional views of the process of the conventional method, Figure 2 is a top view showing a state in which mask alignment is automatically performed using alignment keys formed by the conventional method, and Figures 3A to D are sectional views of the process of the present invention. 1st
4A-4D are process sectional views of the second embodiment of the present invention, and FIG. 5 is a process cross-sectional view of the second embodiment of the present invention, and FIG. 5 is a process sectional view of the second embodiment of the present invention. It is a top view showing a state. 1...Semiconductor substrate, 6...Part of alignment key, 4...Groove, 11...Alignment key area on mask. Names of agents: Jyuju Kon, the late Oo, and one other person Figure 1 Figure 1 Figure 2 Figure 3 Figure 3 Figure 4 Figure 4 Figure 5

Claims (1)

[Claims] A method for manufacturing a semiconductor device, comprising at least the steps of etching a semiconductor substrate to form only one or more alignment keys, and performing alignment using the alignment keys.