JPH02230774A - Insulated gate type semiconductor device - Google Patents

Abstract

PURPOSE:To make a parasitic transistor formed in a protecting element part small, and eliminate the restrictions of a semiconductor substrate by selecting necessary diodes of low breakdown strength among a plurality of junctions having different depths and impurity concentrations, and connecting them in series as the protecting element of an insulated gate type field effect transistor. CONSTITUTION:A DSA type MOS-FET 31 and diodes as a protecting element are formed on a common semiconductor substrate: two pairs of bi-directional connection diodes are connected in series between the source S and the gate G of the DSA type MOS-FET. According to this constitution, P<+> type regions 22, 23 of high surface concentration are deeply formed, so that hFE of a parasitic transistor can be made small. The breakdown strength of the diodes as a protecting element becomes a voltage VEB between emitter.base corresponding with the parasitic transistor, and the value is low. As a result, the manufacturing in response to the breakdown strength of the MOS-FET is enabled by connecting diodes of a plurality of constitutions in series.

Description

[Detailed Description of the Invention] [Summary of the Invention] Semiconductor devices, particularly double diffusion (DSA)
Regarding an insulated gate semiconductor device in which a vertical insulated gate field effect transistor by sedSelf-^1ignment is provided with a protection element for preventing electrostatic discharge damage and control system destruction, hy of a parasitic transistor formed by the protection element. The purpose of the present invention is to provide an insulated gate semiconductor device equipped with a protection element that can reduce the 't, is not limited by the thickness of the semiconductor substrate, and can improve performance. On a separate substrate, a necessary number of protection elements are connected in series to the insulated gate field effect transistor, with the necessary low voltage diodes selected from among multiple diodes formed by junctions with different depths and impurity concentrations. The structure includes an insulated gate type semiconductor device connected to each other.

[Industrial application field]

The present invention relates to semiconductor devices, particularly double diffusion (DSA)
The present invention relates to an insulated gate type semiconductor device in which a vertical insulated gate field effect transistor (hereinafter referred to as a DSA type MOSFET) by fused self-alignment is provided with a protection element for preventing electrostatic discharge damage and control system destruction.

[Conventional technology] In the conventional DSA type MOS-FET technology, the channel length is formed by the difference in double diffusion of two impurities, so this channel length can be set sufficiently small, and the MOS-FET has good high frequency characteristics. -FET can be obtained. However, in such a MOS-FET, the gate oxide film has a thickness of about 600 to 1000 nm.
The dielectric breakdown voltage is, for example, about 30V at a film thickness of 600 people. Therefore, this MOS-FET is equipped with a protective element such as a diode within the same chip to prevent electrostatic discharge damage and to prevent destruction of the control IC connected to it.
Or it is provided as a separate chip.

FIG. 6 is a cross-sectional view of a conventional example of a DSA type MOS-FET.
A diode is provided as a protection element.

In the figure, a P-type base region 62 is selectively formed on the surface of an N-type semiconductor substrate 61 by a diffusion method or the like.
Further, a source region 63 is selectively formed in the base region 62 by a diffusion method or the like, and these base regions 62
A channel portion 74 is formed by the difference in lateral diffusion of the source region 63 and the source region 63 . A gate oxide film 64 and a gate electrode 65 are formed on this channel portion 74, and a source electrode 65 is formed on the source region 63 and extends over the base region 62.
6 is formed. In addition, an N-type semiconductor substrate 61 made of an
The type 1 region is a drain region 67, and a low resistivity region 68 is provided on the back side of the N-type semiconductor substrate 31, forming a DSA type MOS-FET. Further, in another region on the surface side of the N-type semiconductor substrate 61, a base region 62 is provided.
The P-type region 6 of the same conductivity type is deeper (for example, about 13 μm).
9 is formed, two P-type regions 70 and 71 with high surface concentration are formed on this P-type region 69 by selective diffusion, and further N-type regions 70 and 71 are formed on these P-type regions 70 and 71, respectively.
Type 4 regions 72 and 73 are formed by selective diffusion.

A protection element having a structure in which two PN junction diodes formed between the N-type regions 72 and 73 and the P-type regions 70 and 71 are bidirectionally connected is connected to the surface of the N-type semiconductor substrate 61. Configured on the side. And N° type region 7
2 and 73 are each DSA type MO S-FET
is connected to the source electrode 66 and gate electrode 65 of.

However, in the DSA type MOS-FET with the above structure, the parasitic transistor Tr+
and Trz occur, these parasitic transistors Tr
．． and the common emitter current amplification factor hFE of T r2 is set to low
At the same time, the breakdown voltage of MOS-FET and protection element is
Parasitic transistor Tr. and Tr2, it is necessary to correlate as follows.

B Vnss < B VCES, B Voss
< BVDG Here, BVoss is the source-drain breakdown voltage of the MOS-FET, BVC is the collector-emitter breakdown voltage of the parasitic transistor, and BVnc is the drain-gate breakdown voltage.

[Problem to be solved by the invention]

Therefore, in the conventional structure, the P type region 69 forming the protection element is deep, about 13 μm, and has a low surface concentration, so that the parasitic transistor Tr. and hF of Trz! Since it is difficult to form a small P-type region 69 and the breakdown voltage control is determined by the P-type region 69, there is a drawback that the correlation with the performance of the insulated gate semiconductor device is limited.
Due to the formation of type 1 region 69, sagging occurs on the back surface and the breakdown voltage deteriorates, resulting in a MOS-FE with BVoss characteristics for low breakdown voltage.
It is difficult to manufacture T.

Therefore, the present invention can lower the hrt of the parasitic transistor formed by the protection element, and is not limited by the semiconductor substrate.
An object of the present invention is to provide an insulated gate semiconductor device provided with a protection element that can improve performance.

[Means to solve the problem]

The above problem is to select a necessary low voltage diode from among a plurality of junctions formed with different depths and impurity concentrations on the same substrate on which an insulated gate field effect transistor is formed or on a different substrate, and to This is achieved by an insulated gate type semiconductor device in which a required number of protection elements connected in series are connected to a gate type field effect transistor.

[Effect]

In the present invention, a necessary low voltage diode is selected from among a plurality of diodes using junctions with different depths and impurity concentrations, and is connected in series as a protection element of an insulated gate field effect transistor. The hFE of the parasitic transistor formed can be made small, and the limitations imposed by the semiconductor substrate can be eliminated.

[Example] Hereinafter, the present invention will be specifically explained with reference to an illustrated example.

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

In the figure, a P-type heath region 12 is selectively formed on the front surface side of an N-type semiconductor substrate 11, as in the conventional example.
Further, an N-type source region 13 is selectively formed in this base region 12, and these base regions 12 and source regions 1
A channel portion is formed by the difference in lateral diffusion of the three portions. A gate oxide film 14 and a gate electrode 15 are formed on the channel portion, and a source electrode 16 is formed on the source region 13 and also extends to the base region 12. Further, the N1 type region made of the N type semiconductor substrate 11 is a drain region 17, and a low resistivity region 18 is provided on the back side of the N type semiconductor substrate l1, and a DSA type M
It constitutes OSFET31.

In addition, a P-type region 19 is selectively formed in another region on the surface side of the N-type semiconductor substrate 11, and its depth is approximately the same as that of the Heath region 12, and the surface concentration is Two N°-type regions 20 and 21 with a high temperature are selectively formed.
Two P' type regions 22 and 23 with high surface concentration are selectively formed. In this way, the N3 type regions 20 and 21
, P3 type regions 22 and 23, and P type region 19 form a plurality of structures in which two PN junctions are bidirectionally connected, and one of them is connected in series to form a low voltage diode as required. Protection element 32 with a structure
is formed on the N-type semiconductor substrate 1l. The N-type nodal regions 20 and 21 are connected to the source electrode 16 and gate electrode 15 of the DSA type MOS-FET, respectively.

FIG. 2 is an equivalent circuit diagram of the semiconductor device in FIG.
The A-type MOS-FET 31 and the diode as the protection element 32 are formed on a common semiconductor substrate, and the DS
Two sets of bidirectionally connected diodes are connected in series between the source S and gate G of the A-type MOS-FET.

According to the above structure, since the P-type regions 22 and 23 with high surface concentration are formed deeply, the hF of the parasitic transistor
E can be made smaller. Further, the diode as a protection element has a low breakdown voltage of an emitter-base voltage V} which corresponds to a parasitic transistor. Therefore, by adaptively connecting diodes of multiple configurations in series, M
It can be manufactured according to the breakdown voltage of the OS-FET. Furthermore, there is no longer a restriction imposed by the semiconductor substrate 1l, and performance can be improved.

FIGS. 3 and 4 are cross-sectional views of a protective element portion according to an embodiment with a different configuration. Note that parts corresponding to those in FIG. 1 are denoted by the same reference numerals.

In the protection element of the example shown in FIG. 3, comparatively deep P-type regions 41 and 42 are selectively formed in the region on the surface side of the N-type semiconductor substrate 11, and the P-type regions 41 and 42 are formed so as to include the P-type region 4L42. A type region 19 is formed, and N-type regions 20 and 21 are selectively formed on the surface thereof. It is connected. The N-type regions 20 and 21 are connected to a source electrode and a gate electrode of a DSA type MOS-FET (not shown), respectively.

In the embodiment shown in FIG. 3, by deepening the P type region 4L42, the N type region 20.21 and the P type region 4L are made deep.
The pressure resistance at the joint of 1.42 mm ensures that it will not be affected by surface shadows. In addition, by making the P type regions 41 and 42 deeper and higher concentration than the P type region 19, N''
The hFE in the -P''-N structure is reduced.
In FIG. 3, the FET channel portion shown in FIG. 1 is omitted. Further, in the protection element of the example shown in FIG. 4, a P° type region 4l is selectively formed on the surface side of the N type semiconductor substrate 11, and a P1 type region 19 is formed to include this P° type region 41. The N° type region 20 is selectively formed, and a shallow high concentration P° type region 76 is formed in a part of the P1 type region 19.

A plurality of these are also formed as described above, and one of them is connected in series as necessary. Furthermore, a configuration in which there is no separate P-type region 41 as shown in FIG. 1 is also conceivable. The N+ type region 20 and the P' type region 76 are connected to a source electrode and a gate electrode of a DSA type MOS-FET (not shown), respectively.

In the embodiment shown in FIG. 4, the junction breakdown voltage is uniquely determined within the substrate as in the embodiment shown in FIG. 3, but the difference is that the P+ type region 76 is simply a contact.

In the configurations shown in FIGS. 3 and 4 above, the hFE of the parasitic transistor is small, as in the first embodiment, and there is no restriction due to the semiconductor substrate 11, making it possible to improve performance.

FIGS. 5(a) to 5(f) show the manufacturing of the semiconductor device according to the embodiment of the present invention. It is a process sectional view and shows the manufacturing method of the protection element and DSA type MOS-FET of 3rd Example. Note that parts corresponding to the above embodiments are denoted by the same reference numerals.

First, as shown in FIG.
An opening is formed in 1 to form a protective element portion, and boron (B) ions, which are P-type impurities, are implanted into the opening.
2. The 2-shaped regions 41 and 42 are selectively formed. These P3
The mold regions 41 and 42 have a surface concentration of 5×10 ”
/cm' with a depth of about 4.5 μm. Then, a Si02 film 52 is formed on the entire surface.

Next, as shown in the same figure (b), M O S-F E T
The SiO2 film 5L52 of the protective element section and the protective element section is opened, B ions are implanted, and heat treatment is performed to form the heath region 12 and the P type region 19 of the MOS-FET section, and the SiO2 film 5L52 is formed on the entire surface.
form 3. This base region 12 has a surface concentration of I
X 10' Il/cm3, diffusion depth 2.7 am
The P-type region 19 has a surface concentration of IX.
IO"/cm3, and the diffusion depth is approximately 4.0 μm.

? As shown in the same figure (C), the Si of the MOS-FET section
The O2 film is opened and the exposed surface of the N-type semiconductor substrate I1 is oxidized to form a gate oxide film 14.

Next, as shown in FIG. 2D, a gate electrode 15 made of polysilicon is formed on the gate oxide film 14.

Next, as shown in the same figure (e), arsenic (
By ion-implanting As) or phosphorus (P), MOSFET
A source region 13 in the part and N-type regions 20 and 21 in the protection element part are formed, and a Sin2 film 54 is formed on the entire surface. The source region 13 and the N-type regions 20 and 21 have a surface concentration of 2×10”/c” and a diffusion depth of 1.
．． It is formed to have a thickness of about 3 μm.

Next, as shown in FIG. 2F, openings for the gate and source are formed, and the gate and N' type region 20 and the source and N' type region 21 are connected by aluminum wiring.

By the above method, a semiconductor device in which a DSA type MOS-FET and a protection element are provided on the same substrate is manufactured.

In the above embodiment, the DSA type MOS-FET and the protection element are provided on the same semiconductor substrate, but the scope of the present invention is not limited to this, and the protection element portion is formed separately.
It is also possible to assemble series-connected substrates and connect a protection element in series between the gate and source of the MOS-FET. It can also be applied as a protection element between the drain and the source.

[Effects of the Invention] As explained above, according to the present invention, the hFE of the parasitic transistor formed in the protection element portion can be reduced, and it can be limited by the substrate, and the performance can be improved. .

[Brief explanation of the drawing]

1 is a sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the semiconductor device of FIG. 1, and FIG. 3 is a sectional view of a protection element portion of a second embodiment of the present invention. FIG. 4 is a sectional view of the protection element portion of the third embodiment of the present invention, FIGS. 5(a) to (f) are sectional views of the manufacturing process of the semiconductor device of the embodiment of the present invention, and FIG. 6 is a DSA of the conventional example. FIG. 2 is a cross-sectional view of a type MOIFET. ? 1 is a MOS-F film T1; 32 is a protection element; 41, 42, and 76 are P' type regions; and 51, 52, 53, and 54 are SiO2 films. In the figure, 11 is an N-type semiconductor substrate, 12 is a base region, 13 is a source region, 14 is a gate oxide film, 15 is a gate electrode, 16 is a source electrode, 17 is a drain region, 18 is a low resistivity region, 19 is a P-type region, 20.21 is N+-type region, 22.23 is P+-type region, Patent applicant Fujitsu Co., Ltd.

Claims (1)

[Claims] On the same substrate on which the insulated gate field effect transistor is formed or on a different substrate, a necessary low breakdown voltage diode is selected from a plurality of junctions formed with different depths and impurity concentrations, and the insulated gate field effect transistor is formed on the same substrate or on a different substrate. An insulated gate semiconductor device consisting of a transistor and a required number of protection elements connected in series.