JPH02230775A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the corner part of a first conductor layer from being pointed sharply, and keep a shape where electric field concentration is not generated by a method wherein, when a third oxide film is formed by thermal oxidation method, a first conductor layer is surrounded by a nitride film positioned in the upper part and a side wall spacer positioned on the side part, thereby cutting OFF the ventilation to the external atmosphere. CONSTITUTION:A part of a first gate oxide film 51 positioned under a side wall polysilicon layer 57a is eliminated, and then thermal oxidation is performed. By this thermal oxidation, a second gate oxide film 50a is formed on the main surface of a silicon substrate 50. In this case, a first polysilicon layer 52 is surrounded by a silicon nitride film 54 positioned in the upper part and a side wall polisilicon layer 57a positioned at a side part, and the ventilation to the external atmosphere is cut off. As a result, the progress of oxidation for the first polysilicon layer 52 is restrained during the thermal oxidation. Hence, even after the thermal oxidation is finished, the side part of the first polysilicon layer 52 keeps a superior shape as it is.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a semiconductor device having a structure in which one conductor layer rides on the other conductor layer. The present invention relates to a manufacturing method. More particularly, the invention relates to a method for improving the shape of the side of one conductor layer located beneath another conductor layer.

[Prior Art] EEFROM (Electrically Erase) is a memory device with a structure in which data can be freely programmed and also electrically written and erased.
asable and programmable
read only memory).

FIG. 4 is a block diagram of the EEFROM.

The EEFROM includes a memory array 1, a row address buffer 2, a column address buffer 73, a row decoder 4, and a column decoder 5. A plurality of memory cells are arranged in the memory array 1. Row address buffer 2 receives a row address signal applied from the outside.

Column address buffer 3 receives a column address signal applied from the outside. Row decoder 4 decodes the address output from row address buffer 2 and activates a word line connected to a specific memory cell. Column decoder 5 decodes the address output from column address buffer 3 and activates Y gate 6, thereby making the bit line connected to a specific memory cell I/O.
Connect to O line. The sense amplifier 7 detects, via the Y gate 6, the data signal stored in the memory cell selected by the row decoder and column decoder. The detected signal is amplified by the sense amplifier and sent out via the output buffer 8. EEFRO
M further includes an input buffer 9 for providing control signals to various circuits associated with the memory array.

Several different types of EERPOM have been proposed. One of these is a flash EEPROM, which is composed of one transistor and can electrically erase information charges written on the entire chip at once. One memory cell of a flash EEPROM is
It has a structure in which the control gate rests on top of the floating gate.

FIG. 5 is an equivalent circuit diagram of one memory cell in a conventional flash EEPROM. FIG. 6 is an equivalent circuit diagram when the memory cell shown in FIG. 5 is used to form a 4-bit configuration. This memory cell is composed of one floating gate transistor.

This transistor includes a control gate 10 connected to a word line WL W2, a source region 11 connected to source lines S1 and S2, a drain region 12 connected to bit lines B1 and B2, and a drain region of the control gate 10. Floating gate 1 formed on the 12 side
3.

Floating gate 13 accumulates charge.

Depending on the voltage applied to control gate 10 and drain region 12, charge is released/injected between bloating gate 13 and a channel region formed in semiconductor substrate 14. As a result, information charges held in floating gate 13 are written and erased. In the case of reading, the transistors are turned on and off in response to signals applied via word lines W1 and W2. Thereby, the information held by the floating gate 13 is transferred to the bit line Bl connected to the drain region 12.
, B2. When writing and reading information, predetermined voltages are applied to necessary bit lines B1 and B2 and word lines W1 and W2.

In the case of erasing, all information is erased at once by applying an erasing voltage to all bit lines B1 and B2.

Figure 7 shows the IEEE Journal of Sol
id-State Circuits, Vol. S.C.
-22, No. 5 (1987, P.676-P.68
3) Conventional one-transistor flash EE shown in
FIG. 3 is a sectional view showing a PROM. The structure of a conventional flash EEPROM will be explained with reference to this figure.

On the main surface of a p-type semiconductor substrate 14 made of silicon single crystal or the like, an n-type source region 11 and a drain region 12 are formed at intervals. These source areas 11
A channel region is formed in the region sandwiched by the drain region 12.

A control gate 10 and a floating gate 13 are formed on this channel region. The control gate 10 has a thick gate oxide film 15 on the substrate 14.
is formed through. Furthermore, the floating gate 13 is formed on the substrate 14 with a thin gate oxide film 16 interposed therebetween.

This floating gate 13 and control gate 1
0, an insulating film 17 is formed.

One end of the control gate 10, which also serves as a word line, is provided so as to be located above the floating gate 13. The other end of the control gate 10 is provided so as to extend over a thick gate oxide film 15 formed on the side surface of the floating gate 13.

In this case, the control gate 10 is formed by mask alignment so that it has a predetermined planar area that overlaps with the floating gate 13. The source region 11 and drain region 12 arranged on both sides of the control gate 10 and the floating gate 13 are formed in a self-aligned manner by doping impurities using the patterns of the control gate 10 and the floating gate 13. Ru.

One end of the control gate 10 overlaps a part of the source region 11 with a thick gate oxide film 15 interposed therebetween, and one end of the floating gate 13 overlaps a part of the drain region 12 with a thin gate oxide film 16 interposed therebetween. A thick interlayer insulating film 18 is provided above the substrate 14 so as to cover the control gate 10 . The thick interlayer insulating film 1
A contact hole 19 reaching a part of the main surface of the drain region 12 is formed in the drain region 8 . Thick interlayer insulation film 1
A wiring layer 20 made of aluminum or the like is formed on top of the wiring layer 8, which also serves as a bit line. The wiring layer 20 is also formed within the contact hole 19 . Thereby, the wiring layer 20 is electrically connected to the drain region 12.

[Problems to be Solved by the Invention] As described above, the memory cell of a flash EEPROM has a structure in which the control gate rides on the floating gate. The inventor of the present application has discovered that there are various problems when manufacturing this riding structure. The problems involved will now be explained with reference to FIGS. 8A to 8F, which illustrate a conventional method for manufacturing a riding structure.

First, with reference to FIG. 8A, on the silicon substrate 3o,
A first gate oxide film 31, a first polysilicon layer 32, a silicon oxide film 33, and a silicon nitride film 34 are formed in order from the bottom. Next, using a mask with the same photoresist pattern created by exposure and development,
The silicon nitride film 34, silicon oxide film 33, and first polysilicon layer 32 are plasma etched in a self-aligned manner (FIG. 8B). The patterned first polysilicon layer 32 serves as a floating gate in a flash EEPROM memory cell.

Next, using the patterned first polysilicon layer 32 as a mask, the first gate oxide film 3 on the silicon substrate 30 is
Wet etching 1. This wet etching removes the silicon nitride film 34 and the first polysilicon layer 3.
The side surfaces of the silicon oxide film 33 located between the silicon oxide film 2 and the silicon oxide film 33 are partially etched away. Similarly, the first gate oxide film 31 located directly under the first polysilicon layer 32
Also, part of it is etched away. As a result, as shown in FIG. 8C, an undercut as shown by arrow A occurs between the first polysilicon layer 32 and the silicon substrate 30, and an undercut occurs between the silicon nitride film 34 and the first polysilicon layer 32. Undercuts as shown by arrow B also occur in between.

Next, by thermally oxidizing the silicon substrate 30, a second gate 5 oxide film 30a is formed on the main surface of the silicon substrate 30.
(Figure 8D). Due to this thermal oxidation, a sidewall oxide film 32 is also formed on the sides of the first polysilicon layer 32.
a is formed. Since the upper part of the first polysilicon layer 32 is covered with the silicon nitride film 34, oxidation progresses slowly at the upper end portions of the sides of the first polysilicon layer 32. On the other hand, oxidation progresses rapidly in the central and lower end portions of the sides of the first polysilicon layer 32 that are far away from the silicon nitride film 34. Therefore, the thickness of the sidewall oxide film 32a is thinner at the upper end portion and thicker at the middle portion. Due to the progress of such oxidation, the shape of the side portions of the first polysilicon layer 32 that is not oxidized becomes thick in the central portion. As a result, as is clear from the structure of the portion surrounded by the broken line circle D in the figure, the upper corner portion of the first polysilicon layer 32 has a sharply pointed shape. - Also, the thickness of the sidewall oxide film 32a located above this sharp corner is thin.

Further, since an undercut A existed between the first polysilicon layer 32 and the silicon substrate 30, even after forming the oxide film on the first polysilicon layer 32 and the silicon substrate 30, the side Four minute portions as shown by arrow C are formed at the portion where the wall oxide film 32a and the second gate oxide film 30a meet.

Next, as shown in FIG. 8E, on the silicon substrate 30,
A second polysilicon layer 35 is deposited.

Next, as shown in FIG. 8F, the second polysilicon layer 35
is patterned into a predetermined shape and becomes a control gate.

Flash E manufactured by the above method
The F ROM memory cell has the following problems.

Referring to FIG. 8F and focusing on the structure of the portion surrounded by the broken line circle D, as described above, the upper corner portion of the first polysilicon layer (floating gate) 32 has a sharply pointed shape. .

Furthermore, the thickness of the sidewall oxide film 32a located above this corner portion is thin. Therefore, the control gate (second polysilicon layer). When a voltage is applied between 35 and floating gate 32, electric field concentration occurs at the upper corner of floating gate 32. In addition to this electric field concentration, since the sidewall oxide film 32a located on the upper corner of the floating gate 32 is thin, the floating gate 32
A problem arises in that the dielectric strength between the control gate 2 and the control gate 35 is significantly reduced.

Patterning of the second polysilicon layer 35 is performed by anisotropic dry etching. At this time, as shown in FIG. 8F, the polysilicon layer that had entered the recess at the boundary between the sidewall oxide film 32a and the second gate oxide film 32a is not etched and remains as a residue 35a. This residue 35a extends in a direction perpendicular to the plane of the paper, and may, for example, electrically connect a plurality of conductor layers and cause a short circuit.

Further, during subsequent manufacturing steps performed after forming the control gate 35, the residue 35a may peel off from the oxide film and become debris that degrades the operating characteristics of the device.

The above-mentioned problems are especially noticeable when manufacturing flash EEPROM memory cells. but,
Similar problems will be pointed out not only in flash EEFROM memory cells but also in devices having a structure in which one conductor layer is placed on top of another conductor layer. For example, similar problems occur in areas where word lines and bit lines intersect three-dimensionally.

An object of the present invention is to provide a method for manufacturing a semiconductor device that can maintain the side portion of one conductor layer located below the other conductor layer in a shape that prevents electric field concentration.

[Means for Solving the Problems] The present invention is a method of manufacturing a semiconductor device having a structure in which one conductor layer rides on the other conductor layer. First, a first oxide film is formed on the main surface of the substrate in order from the bottom.
A first conductor layer, a second M film, and a nitride film are formed. Next, the nitride film, second oxide film, and first conductor layer are patterned into a predetermined shape by etching using a mask.

Next, a sidewall spacer having a height reaching the nitride film and to be an insulating film is formed on the side of the patterned stack of the nitride film, the second oxide film, and the first conductor layer. Next, the first oxide film is wet-etched using the laminate and sidewall spacers as masks.
The first oxide film exposed from the mask is removed.

Next, a third oxide film is formed by thermal oxidation on the main surface of the substrate exposed by wet etching. Next, a second conductor layer is formed on the laminate and the sidewall baser.

[Function] When forming the third oxide film by thermal oxidation, the first conductor layer is surrounded by the nitride film located above and the sidewall spacers located laterally, and communication with the external atmosphere is blocked. ing. Therefore, progress of oxidation on the first conductor layer is suppressed.

This prevents the upper corners of the sides of the first conductor layer from becoming sharply pointed due to oxidation.

[Embodiment] FIGS. IA to IK sequentially show the steps up to making a control gate of a memory cell of a flash EEFROM.

Referring to FIG. IA, a first gate oxide film 51 is formed on the main surface of a silicon substrate 50 by, for example, thermally oxidizing it.

Next, referring to FIG. IB, a first polysilicon layer 52, a silicon oxide film 53, a silicon nitride film 54, and a silicon oxide film 55 are placed on the first gate oxide film 51 in order from the bottom.
Deposit.

Next, by using the photoresist 56 formed into a predetermined shape by exposure and development as a mask, reactive ion etching is performed to form the first polysilicon layer 52 and the silicon oxide film as shown in FIG. A four-layer structure consisting of a silicon nitride film 53, a silicon nitride film 54, and a silicon oxide film 55 is obtained.

The patterned first polysilicon layer 52 becomes the floating gate of the flash EEFROM. 1st
The reason why the silicon oxide film 53 was first formed on the polysilicon layer 52 and the silicon nitride film 54 was formed thereon is as follows.

In the memory cell of flash EEPROM,
The two-layer structure of silicon oxide film 53 and silicon nitride film 54 functions as an insulating film located between the floating gate and the control gate.

In the case of an EEFROM memory cell, it is desirable to increase the capacitance between the control gate and the floating gate as much as possible. The dielectric constant of a nitride film is about twice as high as that of an oxide film. Therefore, if a single nitride film is used to ensure the same capacity as a single oxide film, the thickness of the nitride film can be made approximately twice the thickness of the oxide film. Considering the dielectric strength of the insulating film located between the floating gate and the control gate, it is desirable that the insulating film be thicker.

If the insulating film between the floating gate and the control gate is composed of a single layer of silicon oxide, the thickness of the insulating film becomes too thin, making it impossible to obtain the necessary dielectric strength voltage. On the other hand, when the insulating film is composed of a single layer of silicon nitride film, the film thickness is sufficient and a sufficient dielectric strength voltage can be obtained. However, a silicon nitride film is more susceptible to current leakage than a silicon oxide film. Therefore, when the insulating film is made of a single layer of silicon nitride film, a small current leak occurs when a low voltage is applied between the control gate and the floating gate. For this reason, it is preferable to adopt a two-layer structure of a silicon nitride film and a silicon oxide film as the insulating film located between the floating gate and the control gate. A silicon oxide film with a small thickness prevents leakage of minute currents, and a silicon nitride film with a large thickness contributes to achieving sufficient dielectric strength.

By the way, there is a large difference in thermal expansion coefficient between polysilicon and silicon nitride film. Therefore, when the two are brought into direct contact, distortion occurs due to thermal stress. If a silicon oxide film is placed between polysilicon and silicon nitride film,
The silicon oxide film acts as a pad and absorbs the difference in thermal expansion between the polysilicon and the silicon nitride film. For this reason, it is desirable to first form a silicon oxide film 53 on the first polysilicon layer 52 which is to become a floating gate, and then form a silicon nitride film 54 thereon.

After the steps shown in FIG. 1C, the photoresist 56 is removed (not shown). Next, as shown in FIG. ID, a second polysilicon layer 57 is deposited on the patterned four-layer stack and the first gate oxide film 51. The thickness of the second polysilicon layer 57 to be deposited is made as thin as about 500 Å.

Next, as shown in FIG.
A silicon oxide film 58 is deposited thereon by the CVD method. The thickness of the deposited oxide film 58 is approximately 1500 Å.

Next, as shown in FIG. IF, sidewall oxide films 58a are formed on the sides of the second polysilicon layer 57 by anisotropically etching the silicon oxide film 58.

Next, using the sidewall oxide film 58a as a mask, a second
Anisotropic etching is performed on polysilicon layer 57 (FIG. IG). By this anisotropic etching, the IG
As shown in the figure, L-shaped sidewall polysilicon layers 57a are formed on both sides of the four-layer stack. Sidewall polysilicon layer 57a has a height that reaches silicon nitride film 54.

Next, wet etching is performed in the state shown in FIG. 1G. This wet etching is performed using, for example, a hydrofluoric acid solution. By this etching, the first gate oxide film 51 exposed from the sidewall polysilicon layer 57a is removed. Further, the silicon oxide film 55 on the silicon nitride film 54 and the sidewall oxide film 58a are also removed by etching. This situation is shown in Figure IH.

As shown in FIG. IH, a portion of the first gate oxide film 51 located under the sidewall polysilicon layer 57a is removed by etching. Therefore, arrow E in the figure
As shown, an undercut is formed directly under the sidewall polysilicon layer 57a.

Next, thermal oxidation is performed from the state shown in FIG. IH. As a result of this thermal oxidation, a second gate oxide film 50a is formed on the main surface of the silicon substrate 50, as shown in FIG. Further, this thermal oxidation treatment is continued until the sidewall polysilicon layer 57a is completely oxidized. When the sidewall polysilicon layer 57a is completely oxidized, it becomes a silicon oxide film 57b (FIG. 1I).

In the state shown in FIG.
is surrounded by a silicon nitride film 54 located above and a sidewall polysilicon layer 57a located laterally, thereby blocking communication with the external atmosphere. Therefore, during the thermal oxidation process, the progress of oxidation of the first polysilicon layer 52 is suppressed. Therefore, as shown in FIG. II, even after the thermal oxidation is completed, the side portions of the first polysilicon layer 52 maintain a good shape. In other words, the problem encountered in conventional manufacturing methods, that is, the upper corner portion of the second polysilicon layer 52 having a sharp shape, can be avoided.

Also, by thermal oxidation, the sidewall polysilicon layer 5
7a is completely oxidized, the first polysilicon layer 5
The thickness of the oxide film located above the upper corner portion of 2 is sufficiently large.

Referring to Figure IH, in the preliminary stage of thermal oxidation treatment,
An undercut is formed directly under the sidewall polysilicon layer 57H. Sidewall polysilicon J
The portion of W57a located directly above the undercut protrudes laterally, and its top, side, and bottom surfaces are exposed. Thermal oxidation progresses from these three aspects. Therefore, the rate of oxidation progresses quickly. Furthermore, when the polysilicon layer is oxidized, its volume expands. Part I! As shown in the figure, when the sidewall polysilicon layer 57a is completely oxidized to become a silicon oxide film 57b, the undercut is completely filled. Therefore, there are no minute recesses as seen in FIG. 8D.

After the step shown in FIG. II, a third polysilicon layer 59 is deposited on the silicon substrate 50 (FIG. IJ). The third polysilicon layer 59 is patterned into a predetermined shape by etching (FIG. IK). The patterned third polysilicon layer 59 becomes the control gate of the memory cell of the flash EEPROM.

As shown in FIG. IK, the shape of the side portions of the floating gate (first polysilicon layer) 52 is maintained in a good condition. Therefore, electric field concentration at the upper corner portion of floating gate 52 is alleviated. Furthermore, the silicon oxide film 57b located above the upper corner portion of the floating gate 52 has a large thickness. Therefore, the dielectric strength between floating gate 52 and control gate 59 is improved.

Further, since the fourth part is not formed at the boundary between the oxide film 57b formed on the side of the floating gate 52 and the second gate oxide film 50a, the third polysilicon layer 5
No residue remains after etching 9.

In the embodiments described above, the sidewall polysilicon layer 57a needs to be completely oxidized, so the film thickness and the impurity concentration in the polysilicon are selected to satisfy this condition. .

FIGS. 2A to 2F are cross-sectional views sequentially illustrating manufacturing steps of another method for maintaining a good shape of the side portion of a floating gate. First, referring to FIG. 2A, a first gate oxide film 61 is formed on a silicon substrate 60.
A stack of a patterned first polysilicon layer 62, a silicon oxide film 63, and a silicon nitride film 64 is formed on the gate oxide film 61. The first polysilicon layer 62 constitutes a floating gate in a memory cell of a flash EEPROM.

Next, as shown in FIG. 2B, a second polysilicon layer 65 is deposited on the stack and first gate oxide film 61.

By performing anisotropic dry etching on the second polysilicon layer 65, the first polysilicon layer 65 is
A second polysilicon layer is left on the side of the stack of silicon oxide film 63 and silicon nitride film 64 (FIG. 2C). This remaining second polysilicon layer 65a is called a sidewall polysilicon layer. This sidewall polysilicon layer 65a has a height that reaches the silicon nitride film 64.

Next, the laminate and sidewall polysilicon layer 65
Using a as a mask, the first gate oxide film 61 on the silicon substrate 60 is wet-etched. By this etching, the first gate oxide film exposed from the mask is removed (see Figure 2D) Next, a second gate oxide film is formed by thermal oxidation on the main surface of the silicon substrate 60 exposed by wet etching. Form 60a (Figure 2E)
.

By this thermal oxidation treatment, the sidewall polysilicon layer 65a is also completely oxidized to become an oxide film 65b. Since the first polysilicon layer 62 is surrounded by the silicon nitride film 64 and the sidewall polysilicon layer 65a and is cut off from the external atmosphere, the first polysilicon layer 62 is Progress of oxidation is suppressed. Therefore, after the thermal oxidation treatment,
The shape of the side portions of the first polysilicon layer 62 is well maintained.

Next, as shown in FIG. 2F, a patterned third polysilicon layer 66 is deposited over the stack and second gate oxide film 60a. This third polysilicon layer 66
constitutes a control gate in a flash EEPROM memory cell.

FIGS. 3A to 3G are diagrams illustrating the steps of yet another method for maintaining the shape of the side portions of the floating gate. First, referring to FIG. 3A, the silicon substrate 70
A first gate oxide film 71 is formed on the first gate oxide film 71, and
A patterned stack of a first polysilicon layer 72, a silicon oxide film 73, and a silicon nitride film 74 is formed on the gate oxide film 71.

Next, as shown in FIG. 3B, a thin oxide film 72a is formed on the side surface of the first polysilicon layer 72 by mild thermal oxidation. Conditions for this thermal oxidation treatment must be selected so as to maintain a good side shape of the first polysilicon layer 72.

Next, as shown in FIG. 3C, a nitride film 7 is formed on the stacked body and the first gate oxide film 71 by, for example, the CVD method.
Deposit 5. Next, the nitride film 75 is subjected to anisotropic dry etching to leave the nitride film 75 on both sides of the stack (FIG. 3D). Remaining nitride film 7
5a is called a sidewall nitride film. Sidewall nitride film 75a has a height that reaches silicon nitride film 74.

Next, by performing wet etching using the stacked body and sidewall nitride film 75a as a mask, the first gate oxide film 71 exposed from the mask is removed (
Figure 3E).

Next, a second gate oxide film 70a is formed on the main surface of silicon substrate 70 by thermal oxidation treatment (FIG. 3F). During this thermal oxidation treatment, the first polysilicon layer 72 is surrounded by the silicon nitride film 74 and the sidewall nitride film 75a, and communication with the external atmosphere is blocked.
Progress of oxidation on polysilicon layer 72 is suppressed.

Therefore, the side shape of the first polysilicon layer 72 is maintained well.

Next, a patterned second polysilicon layer 76 is deposited over the stack and second gate oxide film 70a (FIG. 3G). The second polysilicon layer 76 constitutes a control gate in a flash EEPROM memory cell.

Note that in each of the embodiments described above, an amorphous silicon layer may be formed instead of the polysilicon layer. Further, each of the embodiments described above has been described as a process for manufacturing a flash EEFROM memory cell. but,
The manufacturing method described above can be applied not only to flash EEF ROM but also to other devices. In short, the above-described manufacturing method can be effectively applied to any device having a structure in which one conductor layer rides on the other conductor layer.

[Effects of the Invention] As described above, according to the present invention, during the thermal oxidation step performed after forming the conductor layer located below, the conductor layer is surrounded by the silicon nitride film and the sidewall baser. Since communication with the external atmosphere is blocked, progress of oxidation of the conductor layer is suppressed. Therefore, the shape of the side portions of the conductor layer is maintained well, and electric field concentration at the corner portions of the conductor layer is alleviated.

[Brief explanation of the drawing]

Figure IA, Figure IB, Figure IC, Figure ID, Figure IE,
FIG. IF, FIG. IG, FIG. IH, FIG. II, FIG. IJ, and FIG. IK are sectional views sequentially showing an example of the manufacturing process according to the present invention. 2A, 2B, 2C, 2D, 2E, and 2F are cross-sectional views sequentially showing other examples of the manufacturing process according to the present invention. Figure 3A, Figure 3B, Figure 3C, Figure 3D, Figure 3E,
FIGS. 3F and 3G are cross-sectional views sequentially showing still another example of the manufacturing process according to the present invention. FIG. 4 is a block diagram of the EEPROM. FIG. 5 is an equivalent circuit diagram corresponding to one memory cell of a flash EEFROM. FIG. 6 is an equivalent circuit diagram of a 4-bit configuration using the memory cells shown in FIG. FIG. 7 is a cross-sectional view of one memory cell of a flash EEPROM. 8A, 8B, 8C, 8D, 8E, and 8F are cross-sectional views sequentially showing conventional steps for manufacturing a memory cell having the structure shown in FIG. 7. . In the figure, 50 is a silicon substrate, 50a is a second gate oxide film, 51 is a first gate oxide film, 52 is a first polysilicon layer, 53 is a silicon oxide film, 54 is a silicon nitride film, 55 is a silicon oxide film, 56 is photoresist, 57
57a is a sidewall polysilicon layer, 58 is a silicon oxide film, 58a is a sidewall oxide film, and 59 is a third polysilicon layer. In addition, in each figure, the same number indicates the same or equivalent element.

Claims (1)

[Claims] A method for manufacturing a semiconductor device having a structure in which one conductor layer is placed on top of another conductor layer, the method comprising: forming a first oxide film on the main surface of a substrate; forming a first conductor layer on the first oxide film; forming a second oxide film on the first conductor layer; and forming a nitride film on the second oxide film. a step of patterning the nitride film, the second oxide film, and the first conductor layer into a predetermined shape by etching the nitride film, the second oxide film, and the first conductor layer using a mask; forming a sidewall spacer having a height reaching the nitride film and to become an insulating film on the side of the laminate with the conductor layer; and using the laminate and the sidewall spacer as a mask to form the first oxide a step of removing the first oxide film exposed from the mask by wet etching the film; and a step of forming a third oxide film by a thermal oxidation method on the main surface of the substrate exposed by the wet etching. A method for manufacturing a semiconductor device, comprising: forming a second conductor layer on the laminate and the sidewall spacer.