JPH02230797A - Multilayer type printed wiring board - Google Patents

Multilayer type printed wiring board

Info

Publication number
JPH02230797A
JPH02230797A JP5103889A JP5103889A JPH02230797A JP H02230797 A JPH02230797 A JP H02230797A JP 5103889 A JP5103889 A JP 5103889A JP 5103889 A JP5103889 A JP 5103889A JP H02230797 A JPH02230797 A JP H02230797A
Authority
JP
Japan
Prior art keywords
circuit pattern
layer
printed wiring
wiring board
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5103889A
Other languages
Japanese (ja)
Inventor
Tadashi Nonaka
野中 忠司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP5103889A priority Critical patent/JPH02230797A/en
Publication of JPH02230797A publication Critical patent/JPH02230797A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To comparatively easily keep electric insulation for an inner layer circuit pattern layer positioned on the lower side of the bottom of a formed non-penetrating hole, by constituting a multilayer type printed wiring board in the manner in which an inner layer insulator layer in the region correspond ing with the bottom part of the non-penetrating hole to be formed is partly thickened. CONSTITUTION:In order to connect a circuit pattern layer 1a with an electrically connected inner layer circuit pattern 1c, e.g. a third layer circuit pattern 1b, a non-penetrating hole 2 is formed by drill working or the like. The thickness of an inner layer insulator layer 3' of a region corresponding with the bottom part of the non-penetrating hole, that is, the inner layer insulator layer 3' inter posed between the above mentioned third layer circuit pattern layer 1b and the next circuit pattern 1c' is previously constituted so as to be partly thick. As a result, even when there exsist some deviations in the depths of the formed non-penetrating holes 2, electric insulation for the next stage circuit pattern layer 1c' is not damaged.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は多層型プリント配線基板に係り、特に一方の主
面側から非貫通のたとえば、電気的な接続用の孔が形設
される多層型プリント配線基板に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a multilayer printed wiring board, in particular a multilayer printed wiring board in which a non-through hole for electrical connection, for example, is formed from one main surface side. The present invention relates to a multilayer printed wiring board.

(従来の技術) 周知のように回路もしくは回路部品の小形化を目的とし
て、プリント配線基板の多層型化が進められている。す
なわち、片面もしくは両面に所定の回路パターン層を有
すると゛ともに、前記両面(両主面)間に絶縁体層を介
して所要の内層日路パターン層を多層的に配設すること
により、配線密度を上げて回路自体乃至回路部品のコン
パクト化が図られている。しかして、この多層型プリン
ト配線基板においては、多層型化の推進もしくはよりコ
ンパクト化乃至配線の高密度化により、前記内層回路パ
ターン層間に薄い絶縁体層を配設する構成が採られるよ
うになって来ている。また、この種の多層型プリント配
線基板においては、第3図に模式的に示めす如く一方の
主面上の回路パターンW1aとたとえば、3層目の内層
回路パターン層1bとを接続するため、ドリル加工によ
り非貫通の孔2を形設し、その非貫通孔2を介して前記
両回路パターン層1a. lb間を電気的に接続して使
用する場合などしばしばある。なお、第3図において、
1cは前記多層回路パターン層を成す他の内層回路パタ
ーン層、3は前記多層回路パターン層間に介在する絶縁
体層、4は前記非貫通孔2内壁面に設けられ回路パター
ン層1a,lb間を電気的に接続するため、めっきによ
り彼着形成した導体層である。
(Prior Art) As is well known, multilayer printed wiring boards are being developed for the purpose of downsizing circuits or circuit components. In other words, by having a predetermined circuit pattern layer on one or both surfaces and arranging the required inner circuit pattern layer in multiple layers with an insulating layer interposed between the two surfaces (both main surfaces), the wiring density can be increased. The circuit itself and circuit components are becoming more compact. However, in this multilayer printed wiring board, due to the promotion of multilayering, compactness, or higher wiring density, a structure in which a thin insulator layer is disposed between the inner circuit pattern layers has been adopted. It's coming. Furthermore, in this type of multilayer printed wiring board, as schematically shown in FIG. 3, in order to connect the circuit pattern W1a on one main surface to, for example, the third inner circuit pattern layer 1b, A non-penetrating hole 2 is formed by drilling, and both circuit pattern layers 1a. It is often used by electrically connecting between lbs. In addition, in Figure 3,
1c is another inner circuit pattern layer forming the multilayer circuit pattern layer, 3 is an insulator layer interposed between the multilayer circuit pattern layers, and 4 is an insulating layer provided on the inner wall surface of the non-through hole 2 to connect between the circuit pattern layers 1a and lb. A conductor layer formed by plating to form an adhesive layer for electrical connection.

(発明が解決しようとする課題) しかし、上記構成の多層型プリント配線基板の場合には
次のような不都合がある。すなわち、前記のようにたと
えば、回路パターン層1a.lb間を電気的に接続する
ためドリル加工によって、所要の非貫通孔2を形成する
場合相当の注意を払っても、非貫通孔2の深さを所定の
位置つまり、内層回路パターン層1bの位置に精度よく
制御することは事実上困難で、前記第3図に示めすよう
に内層回路パターン層1bの次の内層回路パターン層1
cと非貫通孔2内壁面(底部)に設けられた導体層4と
の間の電気的絶縁を十分に保持し得ない場合がしばしば
あり、信頼性の点で問題がある。
(Problems to be Solved by the Invention) However, the multilayer printed wiring board having the above structure has the following disadvantages. That is, as described above, for example, the circuit pattern layer 1a. Even if considerable care is taken when forming the required non-through hole 2 by drilling in order to electrically connect between lbs. It is practically difficult to accurately control the position of the inner circuit pattern layer 1 next to the inner circuit pattern layer 1b, as shown in FIG.
It is often not possible to maintain sufficient electrical insulation between C and the conductor layer 4 provided on the inner wall surface (bottom) of the non-through hole 2, which poses a problem in terms of reliability.

[発明の構成] (課題を解決するための手段) 本発明は上記事情に対処してなされたもので、絶縁体層
を介して所要の回路パターン層が一体的に重ね合されて
成りかつ、一方の主面側から非貫通の孔が形設される多
層型プリント配線基板でにおいて、前記形設される非貫
通孔の底部に対応する領域の内層絶縁体層を部分的に厚
くしたことを骨子ととするものである。
[Structure of the Invention] (Means for Solving the Problems) The present invention has been made in response to the above-mentioned circumstances, and consists of required circuit pattern layers being integrally stacked via an insulating layer, and In a multilayer printed wiring board in which a non-through hole is formed from one main surface side, the inner insulating layer is partially thickened in a region corresponding to the bottom of the non-through hole to be formed. This is the basic outline.

(作 用) 上記のよう.に木発明に係る多層型プリント配線基板は
、形設される非貫通孔の底部に対応する領域の内層絶縁
体層を部分的に厚《してある。このため、ドリル加工な
とにより前記非貫通孔を形設した場合も、形成した非貫
通孔底部の下側に位置する内層回路パターン層との間の
電気的絶縁も比較的容易に保持し易くなる。
(Effect) As above. In the multilayer printed wiring board according to the present invention, the inner insulating layer is partially thickened in a region corresponding to the bottom of the non-through hole to be formed. Therefore, even when the non-through hole is formed by drilling, it is relatively easy to maintain electrical insulation between the inner circuit pattern layer located below the bottom of the formed non-through hole. Become.

(実施例) 以下第1図および第2図を参照して本発明の実施例を説
明する。第1図は本発明に係る多層型プリント配線基板
の要部を模式的に示した断面図であり、laは一方の主
面上の回路パターン層、■bは前記主面上の回路パター
ン層1aと電気的に接続される内層回路パターン層、I
Cは前記多層回路パターン層を成す他の回路パターン層
、3は前記多層回路パターン層( la. lb, l
c)間にそれぞれ介在する絶縁体層である。ところで、
本発明に係る多層型プリント配線基板においては、前記
回路パターン層1aと電気的に接続される内層回路パタ
ーン層1cたとえば、3層目の回路パターン層1bとを
接続するため、ドリル加工などにより非貫通孔2が形設
されかつ、その非貫通孔の底部に対応する領・域の内層
絶縁体層3゜つまり、前記3層目の回路パターン層1b
とその次の回路パターン層1c’との間に介在させた内
層絶縁体層3゜を予め部分的に厚くした構成を成してい
る。しかして、上記構成の多層型プリント配線基板は、
ドリル加工などにより所要の非貫通孔2が形設され非る
位置および数に対応し、また、所要の非貫通孔2の深さ
などに応じてそれぞれ対応する内層絶縁体層3″の部分
を選択的に厚くしたものを用いる他は通常の多層型プリ
ント配線基板の製造方法によって製造し得る。
(Example) An example of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view schematically showing the main parts of a multilayer printed wiring board according to the present invention, where la is a circuit pattern layer on one main surface, and b is a circuit pattern layer on the main surface. an inner circuit pattern layer electrically connected to 1a;
C is another circuit pattern layer forming the multilayer circuit pattern layer, 3 is the multilayer circuit pattern layer (la. lb, l
c) an insulating layer interposed between them. by the way,
In the multilayer printed wiring board according to the present invention, in order to connect the inner circuit pattern layer 1c electrically connected to the circuit pattern layer 1a, for example, to the third circuit pattern layer 1b, a non-contact structure is formed by drilling or the like. The inner insulating layer 3° in the area where the through hole 2 is formed and corresponding to the bottom of the non-through hole, that is, the third circuit pattern layer 1b.
The inner insulating layer 3° interposed between the circuit pattern layer 1c' and the next circuit pattern layer 1c' is partially thickened in advance. However, the multilayer printed wiring board with the above configuration,
Depending on the position and number of the required non-through holes 2 formed by drilling etc., and the depth of the required non-through holes 2, the corresponding portions of the inner insulating layer 3'' are formed. It can be manufactured by a normal method for manufacturing multilayer printed wiring boards, except that the thickness is selectively increased.

このように構成された多層型プリント配線基板は所要の
非貫通孔2を形設した場合も、前記内層絶縁体層3゛の
対応する部分が選択的に厚くしてあるため、形設した非
貫通孔2の深さ(底面位置)に多少のズレがあっても次
の(次段の)回路パターン層1c゛との間の電気的な絶
縁が容易に損われることもなくなる(確実に所要の絶縁
が保持される)。・したがって、形設した非貫通孔2を
介して前記両回路パターン層1a, lb間をたとえば
、めっきにより形成した導体層4で電気的に接続して使
用する場合なども、安心して実用に供し得ることになる
。
In the multilayer printed wiring board configured as described above, even when the required non-through holes 2 are formed, the corresponding portions of the inner insulating layer 3 are selectively thickened, so that the formed non-through holes 2 are thickened selectively. Even if there is a slight deviation in the depth (bottom position) of the through hole 2, the electrical insulation between it and the next (next stage) circuit pattern layer 1c' will not be easily impaired (it will ensure that the required insulation is maintained). - Therefore, even when the two circuit pattern layers 1a and lb are electrically connected via the formed non-through hole 2, for example, by the conductor layer 4 formed by plating, it can be put into practical use with peace of mind. You will get it.

[発明の効果] 上記のように本発明に係る多層型プリント配線基板は、
形設される非貫通孔の底部に対応する領域の内層絶縁体
層を部分的に厚くしてある。このため、ドリル加工なと
により前記非貫通孔を形設した場合も、形成した非貫通
孔底部の下側に位置する内層回路パターン層との間の電
気的絶縁も容易にかつ、確実に保持しつる。つまり、非
貫通孔を形設し、この非貫通孔内壁面に導体層を配設し
て所要の内層回路パターンとの間の電気的接続を行なっ
た場合も信頼性の高い凹路乃至回路部品を構成しうる。
[Effects of the Invention] As described above, the multilayer printed wiring board according to the present invention has the following effects:
The inner insulating layer is partially thickened in a region corresponding to the bottom of the non-through hole to be formed. Therefore, even when the non-through hole is formed by drilling, the electrical insulation between the inner circuit pattern layer located below the bottom of the formed non-through hole is easily and reliably maintained. Shitsuru. In other words, even if a non-through hole is formed and a conductive layer is placed on the inner wall surface of the non-through hole to make an electrical connection with the required inner layer circuit pattern, a highly reliable recessed path or circuit component can be achieved. can be configured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る多層プリント配線基板の構成例を
模式的に示めす一部断面図、第2図は第1図に示した多
層プリント配線基板に非貫通孔を形設しその内壁面に導
体層を配設した状態を示めす断面図、第3図は従来の多
層プリント配線基板に非貫通孔を形設しその内壁面に導
体層を配設した状態を示めす断面図である。 1a・・・表面回路パターン層 1b・・・非貫通孔底部に対応する内層回路パターンl
c・・・内層回路パターン層 2・・・非貫通孔 3・・・内層絶縁体層 3′・・・非貫通孔底部に対応する内層絶縁体層4・・
・内層回路パターンと接続する導体層出願人     
株式会社 東芝 代理人 弁理士 須 山 佐 一
FIG. 1 is a partial cross-sectional view schematically showing a configuration example of a multilayer printed wiring board according to the present invention, and FIG. Fig. 3 is a cross-sectional view showing a state in which a conductive layer is disposed on a wall surface, and Fig. 3 is a cross-sectional view showing a state in which a non-through hole is formed in a conventional multilayer printed wiring board and a conductive layer is disposed on the inner wall surface. be. 1a...Surface circuit pattern layer 1b...Inner layer circuit pattern l corresponding to the bottom of the non-through hole
c...Inner circuit pattern layer 2...Non-through hole 3...Inner insulator layer 3'...Inner insulator layer 4 corresponding to the bottom of the non-through hole...
・Applicant for conductor layer connected to inner layer circuit pattern
Toshiba Corporation Agent Patent Attorney Saichi Suyama

Claims (1)

【特許請求の範囲】 絶縁体層を介して所要の回路パターン層が一体的に重ね
合されて成りかつ、一方の主面側から非貫通の孔が形設
される多層型プリント配線基板であって、 前記形設される非貫通孔の底部に対応する領域の内層絶
縁体層が部分的に厚くされていることを特徴とする多層
型プリント配線基板。
[Scope of Claims] A multilayer printed wiring board in which required circuit pattern layers are integrally stacked with an insulating layer interposed therebetween, and a non-penetrating hole is formed from one main surface side. A multilayer printed wiring board, wherein the inner insulating layer in a region corresponding to the bottom of the formed non-through hole is partially thickened.
JP5103889A 1989-03-03 1989-03-03 Multilayer type printed wiring board Pending JPH02230797A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5103889A JPH02230797A (en) 1989-03-03 1989-03-03 Multilayer type printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5103889A JPH02230797A (en) 1989-03-03 1989-03-03 Multilayer type printed wiring board

Publications (1)

Publication Number Publication Date
JPH02230797A true JPH02230797A (en) 1990-09-13

Family

ID=12875634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5103889A Pending JPH02230797A (en) 1989-03-03 1989-03-03 Multilayer type printed wiring board

Country Status (1)

Country Link
JP (1) JPH02230797A (en)

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