JPH02230821A - Clock generator and information processing system using the same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application in Industry] The present invention relates to a clock generation circuit, and more particularly to a clock generation circuit for a semiconductor integrated circuit device incorporating an information processing device in which logical operations are performed based on a crosshair.

[Conventional technology]

In information processing devices that perform logic operations based on clocks, it is important to manage clock timing in order to prevent internal logic errors and increase speed. In particular, when there are multiple information processing devices, it is desirable that the clocks of each information processing device be synchronized to ensure data transfer between the information processing devices at high speed. Conventionally, as a clock generation circuit that satisfies such requirements, Japanese Patent Laid-Open No. 55
According to the proposal in Publication No. 80137, it is shown that a circuit that generates a clock synchronized with an external signal is used. In addition, as a circuit that generates a clock synchronized with an external signal, IEEJ Journal of Solid State Circuits, SC 22, No. 2 (1987), pages 225 to 261 (IEEE
Journal of Solid-State Cir
caits, Val. SC-22, Nu2 (1987
) p. p. 225-261) and JP-A-58-1846
In Publication No. 26, a phase lock loop (hereinafter abbreviated as PLL:
Phase Locked Looρ).

FIG. 2 shows a block configuration of a conventional clock generation circuit using this PLL. The clock generation circuit 10 includes a phase comparator 11, a low pass filter (LPF) 12, a voltage controlled oscillator (VCO) 13, and a frequency divider 14. The output generated by this phase difference is smoothed by the LPF 12 and given as a control signal for the ■C○13. The VCO 13 is a feedback system that increases or decreases the oscillation frequency according to the output of the LPF 12, divides the oscillation output by a frequency divider 14, and outputs the result as a synchronized clock signal. When the phase of the timing signal is ahead of the phase of the synchronous clock signal, the phase comparator 11 detects the phase difference and operates to increase the frequency generated by the VCO 13 via the LPF 12. As the oscillation frequency of vC○13 increases, the frequency of the synchronized clock signal increases, so the phase of the synchronized clock signal advances and operates to reduce the phase difference with the timing signal. Conversely, when the phase of the timing signal lags behind the phase of the synchronous clock signal,
Since it operates to delay the phase of the synchronous clock signal, the phase difference between the timing signal and the synchronous clock signal is similarly small. In other words, the PLLIO operates to synchronize the phases of the timing signal and the synchronized clock signal and to match the frequencies, thus fulfilling the role of automatic frequency control.

By the way, various circuit configurations have been proposed for each of the units 11 to 14 that make up the PLLIO, and they are used depending on the overall performance.

■C○13 has an internal capacitance (sometimes parasitic capacitance), and controls the charging and discharging current of that capacitance according to the input voltage, thereby changing the time constant and adjusting the oscillation frequency. Generally, the circuit configuration is determined. However, there is a restriction that the charging/discharging current of the capacitor can only be changed within a certain range, and therefore the variable range of the oscillation frequency is also limited within a certain range.

The reason for this restriction will be explained in more detail below. PLLIO operates so that the phase of the timing signal and the phase of the synchronous clock signal match, so even when the frequency of the synchronous clock signal is an integer multiple of the frequency of the timing signal or its reciprocal, the timing signal and the synchronous clock signal The phases of may match. In this case, since there is no phase difference between the two, the PLLIO is in an equilibrium state and pseudo-pulling occurs. To prevent this, v in PLLIO
It is necessary to limit the oscillation frequency of C○13 to a certain range in which pseudo-pulling does not occur. Further, when the oscillation frequency range of the VCO 13 is wide, the change in the oscillation frequency with respect to a change in the input voltage becomes large, so that the loop gain of the PLLIO becomes large.

If the loop gain of PLLIO is large, the noise band of PLL10 will also be high. PLLIO operation becomes unstable. Therefore, it is common practice to set the variable range of the oscillation frequency of the VCO 13 within a certain range.

[Problem to be solved by the invention]

Here, the problems of the above-mentioned conventional technology will be explained. Second
In the PLLIO shown in the figure, a feedback system consisting of each section 11 to 14 realizes synchronization between the timing signal and the synchronous clock signal and frequency matching. However, as described above, the frequency of the synchronous clock signal depends on the oscillation frequency of the VCO 13, and can only be changed within a range corresponding to the frequency range in which the VCO 13 oscillates. Therefore, if the frequency of the timing signal exceeds the frequency range of the synchronized clock signal that corresponds to the frequency range in which the VCO 13 oscillates, the PLLIO cannot operate, causing the problem that the clock synchronization between the information processing devices is lost. .

An object of the present invention is to provide a clock generator having a wide frequency range that can generate a synchronous clock signal by following an externally input timing signal whose frequency changes over a wide range.

[Means to solve the problem]

The above object has a phase comparison means and a voltage controlled oscillation means for generating a frequency signal according to an output level of the phase comparison means, and compares the phase of the oscillation frequency signal with a timing signal input from the outside. In the clock generating device configured to output a synchronized clock signal synchronized with the timing signal, the clock generator includes compensation means for inputting the timing signal and changing the range of the oscillation frequency of the voltage controlled oscillation means in accordance with the frequency of the timing signal. This can be achieved by providing

[Effect]

The compensation means changes the frequency range in which the voltage controlled oscillation means oscillates to a higher frequency when the frequency of the timing signal is high. As a result, the frequency range of the synchronous clock signal of the clock generation circuit also changes to a higher frequency, so that it is possible to prevent the frequency of the timing signal from falling outside the frequency range of the synchronous clock signal. Conversely, when the frequency of the timing signal decreases, the compensating means operates to change the frequency range of the synchronous clock signal to a lower frequency. In other words, since the frequency range of the synchronous clock signal is changed according to the frequency of the timing signal, it is possible to prevent the clock generation circuit from becoming inoperable.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block configuration of a first embodiment of the present invention.

As shown in the figure, this embodiment is a clock generation circuit 20 using a PLL, and parts with the same symbols as those in the conventional example in FIG. 2 have the same functions and configurations. The difference from the conventional example shown in FIG. 2 is that a compensation circuit 15 is provided which inputs a timing signal ST and changes the frequency range in which the VCO 13 oscillates in accordance with the timing frequency fT. The compensation circuit 15 receives a timing signal S
As the frequency f of T increases, VCO 1 increases accordingly.
A signal Sc for changing the oscillation frequency range to a higher frequency at 3° is output. Conversely, when the frequency fT of the timing signal ST becomes lower, a signal SC is outputted to the VCO 13 to change the oscillation frequency range to a lower frequency. The synchronous clock signal CP is a signal obtained by dividing the oscillation output signal Cpo of the VCO 13 by the frequency divider 14. Therefore, the frequency range of the synchronous clock signal cp is proportional to the oscillation frequency range of the VCO 13. In this way, according to this embodiment, depending on the frequency fT of the timing signal ST,
Since the range of the frequency fc of the synchronous clock signal changes,
The frequency fT of the timing signal ST falls within the frequency range of the synchronous clock signal Cp, and as a result, the timing signal S
A synchronous clock signal C that is synchronized with T and has the same frequency.
p can be obtained. Therefore, according to this embodiment, it is possible to realize a clock generation circuit with a wide frequency range that can respond to frequency changes in the timing signal ST. In addition, VCO
Specific examples of the compensation circuit 13 and the compensation circuit 15 will be described later (FIGS. 10, 11, and 15).

FIG. 3 shows an example of a chip configuration of an information processing LSI incorporating the clock generation circuit 20 of FIG. 1. In FIG. L.S.
The I-chip 310 includes a clock circuit 22 including a clock generation circuit (CPG) 20 and a clock distribution circuit 21, and logic circuit blocks 311 to 315 controlled by a clock signal cp that is an output of the clock circuit 22.

CPG20 is a timing signal S input from outside the chip.
A synchronous clock signal CP that receives T and is synchronized with that signal.
The distribution circuit 21 generates a clock signal for controlling each block 311 to 315. Here, the clock signal Cp is a signal delayed by the delay in the distribution circuit 21 from the timing signal ST. but. The LSI chip 310 operates almost in synchronization with the timing signal ST. This causes the LSI chip 310 to connect to the local bus 1.
When transmitting and receiving data via the system bus 102 and the system bus 102, the system has the advantage of being able to operate synchronously with other systems based on a common timing signal.

FIG. 4 shows a configuration diagram of a second embodiment of the present invention. As shown in the figure, the block configuration of the clock circuit 25 includes a clock generation circuit using a PLL. Components with the same reference numerals as in FIGS. 1 and 2 have the same functions and configurations. In the same figure, the difference from the embodiment in FIG. It lies in being. According to this embodiment, it is also possible to compensate for the delay caused by the clock distribution circuit 21, and the logic blocks 311 to 315 explained in FIG.
clock signal can be synchronized with an external timing signal ST. Note that the cause of the delay caused by the distribution circuit 21 is that a large number of buffers are used for distribution. This delay is, for example, 2 to 3 msec.

FIG. 5 shows an example of a chip configuration of an information processing LSI incorporating the clock circuit 25 shown in FIG.

The same reference numerals as in FIG. 3 indicate the same parts. In this embodiment, since the timing signal ST and the clock signal CP are synchronized by the clock circuit CLK25, the LSI chip 3
10 operates in synchronization with a timing signal, and performs completely synchronous operation when transmitting and receiving data to and from other LSI chips via the local bus 101 and system bus 102.

FIG. 6 shows an example of an information processing system using the information processing LSI shown in FIG. 3 or 5. The information processing LSIs 310, 320, and 330 have a built-in clock circuit 22 or 25. Each clock circuit 22 or 25 is controlled by a common timing signal output from a timing signal generation circuit 40. Therefore, each LS I
The clock signals Cp that control the logic circuit blocks in 310, 320, and 330 are all synchronized. Data transfer via the local bus 101 and system bus 102 is synchronized between LSIs, and data transfer can be ensured. In addition, by ensuring data transfer, it becomes possible to increase the speed and realize a high-speed information processing system.

Here, specific embodiments of each block portion constituting the embodiments of FIGS. 1 and 4 will be described with reference to FIGS. 7 to 16.

FIG. 7 shows an embodiment of the phase comparator 11. As shown, it is composed of gate circuits of inverters 701, 702, 712 to 715, 2 manual NANDs 703 to 708, 3 manual NANDs 710 and 711.4 manual NANDs 709. As a result, the phase difference between the rising edges of the timing signal ST and the synchronized clock signal Cp can be determined by the output signals PP, NP, which have the waveform of the time chart shown in FIG.
This is a frequency/phase comparison type phase comparator that converts into PD and ND pulse widths and outputs them. In this embodiment, the inverter 7
14 and 715 output differential pulses. When the phase of the timing signal ST is ahead of the phase of the synchronous clock signal Cp, a pulse signal having a pulse width corresponding to the phase difference is output to the signals PP and NP, as shown in (A) in the figure. On the other hand, if you are behind, please use (C) in the diagram.
It is output to signals PD and ND as shown in . A synchronized state occurs when the rising edges of the timing signal ST and the synchronized clock signal Cp match, and the output does not change as shown in (B) in the figure. That is, in this embodiment, the timing signal ST
The phase difference between the clock signal Cp and the synchronized clock signal Cp is converted into a pulse width of a differential output and output.

FIG. 9 shows an embodiment of the low pass filter (LPF) 12. As shown in the figure, the LPF has a charge pump circuit 90.
1 and a loop filter 917.

In the charge pump circuit 901, symbols 904 to 90
7 is a PMOS, 908 to 916 are NMOS, 902 is a resistor, and 903 is an NPN transistor. PMOS906 and 907, and NMOS9
09 and 910(7) each current is set equal. In other words, PMOS904, 906 and 907, PMOS90
4 and 905, NMOS 908, 909, and 910, and is controlled by the current flowing through the resistor 902 by the bias V^ of the transistor 903.
NMOS 912 and 911, NMOS 914 and 913 are controlled by differential output signals PP and NP, PD and ND of phase comparator 11. These NMOS912 and 911,N
MOS914 and 913 are PMOS907 and NMOS9
This is a switch that switches the current of 10 between output VB and internal current. Therefore, when the NMOS 912 is on, that is, the signal pp is "H" and the signal NP is "L", VaL, l
．． Inject current into PMOS907. On the other hand, NMO S9
14 is on, that is, the signal PD is "H" and the signal ND is "H".
When the current is "L", the current of NMOS910 is extracted from Va. This converts the output pulse of the phase comparator 11 into a pulse current flowing through Va. On the other hand, the NMOS 916 is controlled by the signal NP, and when the NMOS 912 is off, that is, the signal PP is "L" and the signal NP is "rH", the PMOS
907 current through NMOS9 1 1
Lead to 09. On the other hand, NMOS915 is controlled by signal ND, and NMOS914 is off, that is, signal PD is rI.
, J and the signal ND is r}{J. The current of PMOS906 is guided to NMOS910 via NMOS913. Therefore, the current of PMOS907 and NMO S910 is
Since the current always flows even when the current is not output to Va, the potential of their drains can be kept constant. As a result, noise current generated due to charge sharing during switching between NMOS 912 and 914 can be eliminated.

In this way, the charge pump circuit 901 is connected to the phase comparator 1.
Since a pulse current equal to the output pulse width of 1 can be output, charge injection or bow extraction proportional to the pulse width can be realized.

The loop filter 917 is composed of a series circuit of a resistor 918 and a capacitor 919, and converts the pulse current of the charge pump circuit 901 into a voltage by integrating it.

In this way, when the low-pass filter 12 has pulse outputs of the signals PP and NP, the charge pump circuit 90
1 injects charge into the loop filter 917, Va
When the potential of increases and there is a pulse output of the signals PD and ND, the charge pump circuit 901 switches to the loop filter 917.
Since the charge is extracted from Va, the potential of Va decreases.

As a result, the pulse signal corresponding to the phase difference is converted into a voltage.

FIG. 10 shows an embodiment of the voltage controlled oscillator (VCO) 13. As shown in the figure, a voltage/current conversion circuit 1001.
It is configured with a current controlled oscillator 1002 and a level conversion circuit 1003. The voltage/current conversion circuit 1001 receives the current control signal c from the compensation circuit 15, converts the output voltage VB of the low-pass filter 12 into a current control signal Io, and outputs the current control signal Io to the current control oscillator 1002. As a result, the current controlled oscillator 1002 oscillates at a frequency according to IO and outputs a signal Va with a low voltage amplitude. Level conversion circuit? 003 amplifies v2 to the full amplitude signal VF and outputs it. FIG. 11 shows an embodiment of the voltage/current conversion circuit 10o1 shown in FIG. 10. NMOS1101 and ll02, 1103
is a current mirror, and NMOS1102 and 1
The electric current flowing through 103 and electric current 2 have a proportional relationship with IC, and can be expressed by the following equation.

■yo=n1・IC...(1)I
, = nt・Ic...(2
)on the other hand. NMOS1104 and ll05 are a differential pair,
In relation to the level of potential between the reference voltage VR and Va, ■■ is divided. Here, the current of NMOS1104 is PMOS1106
flows to The PMOS 1106 and 1107 are current mirrors, and when the currents flowing through them are set equal, the current of the PMOS 107 becomes equal to that of the NMOS 1104.

By the way, considering the case where the potential of Va is higher than VR,
NMOS1105(7) current is larger than NMOS1104. However, PMOS1107 is NMOS110
Since only a current equal to 4 can be supplied, the current of the difference will be supplied from the circuit of PMOs 1108 and NMOs 1103. Therefore, the current flowing through the PMOS 1108 is larger than the current flowing through the PMOS 1108. vice versa. When the potential of Va is lower than VR, the current of NMOS1105 is NM
Although it is smaller than OSI104, PMOS1107 is N
Since it supplies a current equal to MOSll04, NMOS
The extra current other than the current flowing into 1105 is the PMOS
It is poured into the circuit of 1108 and NMOS1103, and the
becomes smaller than I2. In other words, engineering. The value increases or decreases depending on the magnitude of Va, centering on the force 2. The increase/decrease width at this time is based on the bias current of NMOSIs 104 and 1105, and the following formula holds true.

I2+I1≧Eng, ≧I2−I, ...(3
) By the way, since the PMOSs 1108 and 1109 are current mirrors, the output currents ID and I of the voltage/current conversion circuit 1001 have a proportional relationship, and can be expressed by the following equation.

In=n, + I, − (4)
From the above equations (1), (2), (3), and (4), the following equation holds true.

n 3 (n 2 ” nt ) I C≧In≧
n3(n2-nx) rC +.+ (5) Therefore, the voltage/current conversion circuit 1001 operates within the range where formula (5) holds true. As the potential of Va increases, Io increases, and V
When the potential of a becomes lower, In becomes smaller. Also, the range in which IO changes depends on the IC current, and I
When C is increased, the center of the Io current range moves to the larger side, and when Ic is reduced, the center of the In current range moves to the smaller side. FIG. 12 shows an embodiment of the current controlled oscillator 1002.
As shown, NMOS1201 to 1203, capacity 1
204, NPN transistor 1205, 1206, 12
11, 1212, PMOSI207, 1208, diode 1209, 1210, current source 12.13.1214
It consists of This oscillator 1002 connects the input and output of a switching circuit consisting of bipolar transistors 1205 and 1206 and PMOSs 1207 and 1208 as load elements to a transistor 1211 and a current source 1213.
and a transistor 1212 and a current source 1214.
The current flowing through 205 and 1206 is NMOS12.
This is an emitter-coupled multivibrator configured to be controlled by 02 and 1203. Diode 1209.1210
is a clamp element that limits the amplitude, and the amplitude of VE differentially outputted via the level shift circuit becomes VBE. Also,
NMOS1201, 1202, and 1203 are current mirrors. Therefore, NM○S1202 and 12
If the current flowing through 03 is set to be equal to <I, then ■. is in a proportional relationship with the output current Io of the voltage/current conversion circuit 1001, and can be expressed by the following equation.

I4= n4・Io −
(6) The oscillation frequency fO of such an emitter-coupled multivibrator can be expressed by the following equation, assuming that the capacitance of the timing capacitor 12o4 is Co.

From equations (6) and (7), the following relationship is obtained.

That is, the current controlled oscillator 1002 outputs an oscillation frequency proportional to In.

By the way, since IO has the current range of equation (5), the oscillation frequency fO above also has a frequency range, and (5), (8
), the following formula holds true.

In this way, the center of the frequency range of the oscillation frequency fo is I
When c increases, the frequency moves toward higher frequencies, and conversely, when IC decreases, the frequency shifts toward lower frequencies.

In the embodiment shown in FIG. 12, the NPN transistor 12
PM081207 for switching element of 05.1206
, 1208 load elements constitute a switching circuit, and P
MOS1207, 1208 (7) gates are each NP
Connected to the bases of N transistors 1205 and 1206. This allows the NPN transistor 1205.12
When 06 is on, the impedance of PMOS1207 and 1208 is increased to ensure sufficient amplitude, and conversely, NPN
PMO when transistors 1205 and 1206 are off
The impedance of S1207 and S1208 is lowered to increase the rise speed. therefore,
Even when the current in the switching circuit is small, sufficient amplitude can be ensured, and conversely, even when the current is large and the frequency becomes high, the output rises quickly and can operate satisfactorily, allowing a wide range of oscillation frequencies.

FIG. 13 shows an embodiment of the level conversion circuit 10o3.

As shown. PMOS1301, 1302, 1304
, 1306.130B, 1309, 1312, 1313
, NMOS1303, 1305, 1307, 1310,
1311, 1314, and 1315. The circuit consisting of MOS 1301 to 1307 is an MO whose input is the differential output VE of the current control oscillator 1002 in the previous stage.
MOS1305, which is the bias current source of the ratio type inverter circuit consisting of MOS1304 and 1305, MOS1306 and 1307, is the circuit output of 81301 to 1303.
and the MOS1307 (7) gate, the logic threshold of the ratio inverter circuit can be set at the center of the differential VE, thereby reliably amplifying the amplitude of Vε. MOS1308~1311 and MO31312~
The circuit consisting of the 1315 is a push-pull type inverter circuit using a CMOS current mirror, and amplifies differential signals to single-ended dual amplitudes. Also, MO8130
The circuit consisting of MO8-1311 and MO81312-1315 realizes a differential full amplitude output VF (CPO) by reversing the input connections. In other words, the level conversion circuit 1003 converts the current controlled oscillator 10 by two-stage amplification.
The low voltage differential output VE of 02 is level-converted to a differential output VF of both amplitudes that allows the logic gate circuit to operate.

FIG. 14 shows an embodiment of the frequency divider 14. Clocked inverter gate circuit 1404, 1406, 1407, 1
409 and a feedback latch circuit 1401, ? by inverter gate circuits 1405, 1408? 402,
By controlling these signals to have opposite phases using the differential output VF of the level conversion circuit and providing negative feedback through the inverter gate circuit 14o3, the frequency of VF is divided into 1/2 and output as the synchronous clock signal Cp. It has become.

FIG. 15 shows an embodiment of the compensation circuit 15. Frequency divider 15
01 outputs an output signal ai obtained by dividing the frequency ft of the timing signal ST by 172. This signal a is PMOS
It is input to the gates of NMOS 1503 and NMOS 1504, thereby controlling the charging and discharging of capacitor 1505, and thus constitutes an integrating circuit. The potential a2 of this capacitor 1505 is input to the input terminal of the comparator 1501. A current source 1506 and diodes 1507 to 1 are connected to one end of the comparator 1501.
From a bias circuit consisting of a 5o9 series circuit, 3XVB
E! The potential a3 of is input. The comparator 1501 compares the input potentials a2 and a3, and outputs an output signal a4 having both amplitudes. This signal a4 is input to the gates of PMOS S1512 and NMOS1513. These switching elements are current source 1
511 and 1514 are connected in series to form a charge pump circuit. The output signal a of this charge pump circuit is applied to the capacitor 1515, thereby controlling the charging and discharging of the capacitor 1515. Furthermore, a5 is input to a low-pass filter circuit consisting of a resistor 1516 and a capacitor 1517, thereby smoothing the potential of the capacitor 1515. The output voltage aG of the low-pass filter circuit is input to the gate of NMOS1518. This NMOS1518 is the PM of a current mirror circuit consisting of PMOS1502, 1519, and 1520.
It is connected to O°81519. This current mirror circuit has an electric current flowing through the NMO81518 in response to the signal aG. and the compensation circuit 1 flowing through PMOS 1 5 20
5 output current IC, and a charging current IC with a capacity of 1505. It is designed to be proportionate.

FIG. 16 shows a timing chart of potentials at various parts related to the operation of the compensation circuit 15. Note that in the figure, timing signals a1 and a4 indicate logic levels. Here, PMO
The current flowing through S1502 is connected to the rst current sources 1511 and 15.
The currents flowing through 14 are respectively , and I,, PMOS 1
5 1 The current flowing through 9 and 1518 is Il1 capacity 15
If the capacitances of o5 and 1515 are Ce and C2, respectively, and the frequency of the timing signal ST is fr, then the period t0 can be expressed by the following equation, where the signal a1 is the timing signal St divided by 1/2 by the frequency divider '1501. Since it is a frequency-divided output, it is a signal with a duty of 50%, and the "H" and "L" periods are both t. It is. On the other hand, when a1 is "L", the potential of signal a2 changes from PMOS 1502 to PMOS 150.
3 is at "H", the NMOS 1504 rapidly discharges the capacitor 1505 to the ground level. The comparator 151o compares the potentials of a2 and 83, and the signal a4 becomes "L" when a2 is higher than a, and becomes "L" when a2 is lower than a.
H”. Here, a4 is “H” because of 3VBH of a.
'' is because a1 reaches the potential of [
This is the time it takes for the capacitor 1505 to start discharging after reaching 'H'.

Therefore, when aL is rlJ, a1 rises and 3・VB
If the time it takes to reach the potential of H is t, then a4 becomes r
The time required to reach "H" is given by the following formula.

j, = t, -t, ... (11)
t0 can be expressed by the following formula.

Further, if the time when a4 becomes "L" is t, then the following equation holds true.

1,=10+11...(13)
From equations (10) to (13), t2 and t are expressed by the following equation.

That is, as ■ becomes larger, t2 becomes larger and t3 becomes smaller, and conversely, when . As t2 becomes smaller, t2 becomes smaller and t becomes larger.

Also, the potential of a is PMOS1512 and NM○S151
A4, which controls a charge pump circuit comprising 3, is determined by a4. That is, when a4 is "L", the capacitance C2
1515, the current source 1511 rises at a slope. On the other hand, a
4 is "H", the capacitor C, 1515 is connected to the current source 151
4 falls NMOSI.

In addition, a6 is the potential of aS with a resistor 1516 and a capacitor 1517.
This is the potential smoothed by a low-pass filter circuit. Therefore, when the capacitor C:21515 is charged and discharged, if the charged charge is greater than the discharged charge, the potential of a6 will rise, and if it is less, the potential of a will fall. Here, C. Charge charge Qp in 1515 charge/discharge cycles
and discharge charge Qo can be expressed by the following formula. From the above equations (14) to (16), Qp and Qo can be expressed by the following equations.

In other words, as - ■ becomes larger, Qp becomes smaller and Qo
increases, so it operates in the direction of lowering the potential of a. On the other hand, when Q becomes smaller, Qp becomes larger and Qo becomes smaller, so that it operates in the direction of increasing the potential of a6.

On the other hand, since the potential of a6 is the bias voltage of the NMOS 1518, if the potential of ali increases, the potential of a6 increases. increases,
If the potential of a6 decreases, decreases.

Since PMOS l519 and 15o2 are current mirrors, Ic and Ig are in a proportional relationship and can be expressed by the following equation.

IC=n5・Eng. -(1g)Is
= n,j! , − (19
) Therefore, if the potential of a6 increases, IS increases,
If the potential of aG decreases, Is decreases. That is, this embodiment constitutes a negative feedback loop, and when the potential of a6 is high, is large <, Is is also large.

If Is is large, the potential of a2 will rise quickly, so t2
If m t2 is large, the discharge charge of a becomes large, so that the potential of a is lowered. Conversely, if the potential of aG is low, a. works to increase the potential of In this way, this negative feedback loop becomes balanced when the charges Qp and Qo of charging and discharging as become equal. Therefore, if Qp=Qo in equation (17), the following equation holds true. As mentioned above, the compensation circuit 15 is provided with a negative feedback system that flows an integral current proportional to the frequency fT of the input timing signal ST. The configuration includes means for outputting an output current proportional to the integrated current, thereby forming a frequency/current conversion circuit that outputs an output current Ic proportional to the frequency f of the timing signal ST.

Here, the voltage controlled oscillator 1 shown in FIGS.
The combined operation of 3 and the compensation circuit 15 shown in FIG. 15 will be described. The output current Ic of the compensation circuit 15 and the frequency range of the oscillation frequency fo of the voltage controlled oscillator VC○13 have the relationship shown in equation (9) above. On the other hand, the frequency ft of the timing signal ST and the output currents Ic and n are as described above (21
) because there is a relationship between the expressions. The following formula holds true for fO and ft.

From equations (18) to (20), the output current I of the compensation circuit 15
c is the following formula. In other words. The range of the oscillation frequency of the VCO 13 is determined by the compensation circuit 1.
5 can be determined by the frequency fT of the timing signal ST. If the frequency ft of the timing signal increases, the frequency range of the VCO 13 also increases, and conversely, if it decreases, it similarly decreases.

By the way, in the clock generation circuit 2o of FIG. 1, the frequency fT of the timing signal and the frequency EC of the synchronous clock signal are
are controlled so that they are equal, and the frequency fc of the synchronous clock signal is determined by dividing the oscillation frequency fo of the VCO 13 by the frequency divider 1.
Since the frequency is divided by 4, the frequency range of the oscillation frequency of the VCO 13 needs to include a frequency that is the reciprocal of the amount by which the frequency ft of the timing signal is divided. Therefore, if each circuit constant is set to form a frequency divider, equation (22) is converted to the following equation.

Therefore, since the frequency range of the oscillation frequency fo always includes the ta frequency N-fT, it is possible to realize a clock generation circuit having a wide frequency range without becoming inoperable. It is possible to respond to variations in the frequency ft of the timing signal.

In addition, in this embodiment, the timing capacitance Co of the VCO 13 is
If and the capacitance C of the integrating circuit of the compensation circuit 15 have the same structure, it is possible to make the capacitance variations the same when manufacturing semiconductor integrated circuits.

As a result, the value of N in equation (23), which is determined by the ratio of C6 and C1, can be kept constant regardless of variations in capacitance.
It is possible to set N accurately.

FIG. 17 shows the current controlled oscillator 1002 shown in FIG.
The structure of one embodiment of the capacitor 1204 related to determining the oscillation frequency fo is shown. Capacitors 17o1 and 1702 have the same structure and the same capacitance value, and are connected to terminal b. + bx is reversed and connected in parallel. That is, when realizing a capacitor on an LSI chip, there is a parasitic capacitance other than between the two terminals of the capacitor. Since this parasitic capacitance has a different size for the terminals b, ,b, when connecting the capacitance, terminal dependence occurs.

Considering the current controlled oscillator 1002, if the two terminals of the capacitor 1204 have different parasitic capacitances, the NMOSI 202 and 12
Even if the same current is drawn in 03, the operating current of the circuit will be different because the current flowing through the parasitic capacitance will be different. As a result, the switching period of the transistors 1205 and 1206 changes, and an oscillation output with a duty of 50% cannot be obtained.

Therefore, as mentioned above, since two capacitors with the same structure and the same capacitance value are connected in parallel, even if the parasitic capacitance between the two terminals of each capacitor is different, the overall parasitic capacitance is equal. This has the effect of eliminating terminal dependence. An emitter-coupled multivibrator using this as a timing capacitor has the effect of obtaining an oscillation output with a duty of 50%. FIG. 18 shows a specific structure in which the capacitor 1701 or 1702 shown in FIG. 17 is formed on an LSI chip. 3A is a plan view of the chip, and FIG. 1B is a sectional view taken along line mB-B in FIG. As shown in those figures, a first layer of polyester is formed on a substrate 1801 with an insulating film 18o2 interposed therebetween. A silicon film 1803 is disposed, a second layer polysilicon film 1804 is disposed at intervals on it, and a first layer aluminum film 1804 is further disposed on it.
805 is arranged in layers. and,
The first layer polysilicon film and the first layer aluminum film are connected through a contact hole 1806. And terminal batb
The capacitance between 1 and 1 is, as shown in the equivalent circuit in Figure 19,
The capacitance C1■ between the first layer polysilicon film 18o3 and the second layer polysilicon film 1804 and the second M polysilicon film 18
04 and the capacitance Ci8 between the first layer aluminum film 1805. Note that the parasitic capacitance C at the terminal,
is formed only between the first layer polysilicon film 1804 and the substrate 1801.

In other words, the embodiment shown in FIG. 18 has a structure in which capacitance is formed by stacking the first to third conductor films in a layered manner, so that the parasitic capacitance can be increased without increasing the chip area. This has the effect that it is possible to increase the capacitance without causing any problems.

〔Effect of the invention〕

As explained above, according to the present invention, by the compensation means. Since the oscillation frequency range of the voltage controlled oscillation means in the PLL is changed according to the frequency of the timing signal applied from the outside, even if the frequency of the timing signal changes greatly, the output of the voltage controlled oscillation means It is possible to reliably synchronize a synchronous clock signal with a timing signal.

This makes it possible to reliably synchronize operations related to data processing including data transfer between a plurality of related information processing devices.

[Brief explanation of the drawing]

1 shows a clock generation circuit according to the first embodiment of the present invention, FIG. 2 shows a conventional clock generation circuit, FIG. 3 shows a semiconductor integrated circuit device using the embodiment shown in FIG. 1, and FIG. 4 shows the present invention. Second invention
FIG. 5 shows a semiconductor integrated circuit device using the embodiment of FIG. 2, and FIG. 6 shows an information processing device using the clock generation circuit of the present invention. 7 is a block diagram of one embodiment of the phase comparator 11, FIG. 8 is a time chart for explaining the operation of the phase comparator of FIG. 7, FIG. 9 is a diagram of one embodiment of the low-pass filter circuit 12, and FIG. The figure is an overall configuration diagram of one embodiment of the voltage controlled oscillator 13, FIGS. 11 to 13 are detailed explanatory diagrams of each part of the voltage controlled oscillator in FIG. 10, and FIG. 14 is the configuration of one embodiment of the frequency divider 14. Figure 15 shows compensation circuit 1.
FIG. 16 is a time chart for explaining the operation of the compensation circuit in FIG.
), -(b) are diagrams showing an example of the structure of the capacitor in FIG. 17 on a semiconductor chip, and FIG. 19 is an equivalent circuit diagram of the capacitor in FIG. 18. DESCRIPTION OF SYMBOLS 11... Phase comparator, 12... Low pass filter circuit, 13... Voltage controlled oscillator, 14... Frequency divider, 15...
... Compensation circuit, 21 ... Clock distribution circuit, 22.2
5... Clock circuit, 4o... Timing signal generator, 101... Local bus, 102... System bus, 310, 320, 330... LSI chip, 311
~315,321,322,331...Logic circuit block, 901...Charge pump circuit, 917...Loop filter, 1001...Voltage/current conversion circuit, 1002...Current controlled oscillator, 1003. ... Level conversion circuit, 1801 ... board,
1803...First layer polysilicon film, 1804...
Second layer polysilicon film, 1805... First layer aluminum film, 1806... Contact hole.

Claims (1)

[Claims] 1. Comprising phase comparison means for outputting a signal according to the phase difference between two input signals, and voltage controlled oscillation means for generating a signal with a frequency according to the output signal of the phase comparison means. and a clock generation device which outputs a clock signal based on the output signal of the oscillation means and inputs the clock signal and a timing signal given from the outside to the phase comparison means, the timing signal being input. . A clock generation device, comprising compensation means for changing the oscillation frequency range of the voltage controlled oscillation means in accordance with a change in the frequency of the timing signal. 2. Phase comparison means for outputting a signal according to the phase difference between two signals, voltage controlled oscillation means for generating a signal with a frequency corresponding to the output signal of the phase comparison means, and and a distribution means for converting a clock signal into a plurality of clock signals and distributing the same, and inputting the clock signal outputted from the distribution means and a timing signal given from the outside to the phase comparison means. Device. 3. A phase comparison means for outputting a signal according to the phase difference between two input signals, a voltage controlled oscillation means for generating a signal with a frequency according to the output signal of the phase comparison means, and an output signal of the oscillation means. distribution means for converting and distributing the based clock signal into a plurality of clock signals; and compensation for receiving the timing signal as an input and changing the range of the oscillation frequency of the voltage controlled oscillation means in accordance with changes in the frequency of the timing signal. and a clock signal output from the distribution means and a timing signal given from the outside are input to the phase comparison means. 4. The compensation means has an integration circuit that is set and reset by the timing signal, and has frequency/current conversion means that outputs a current proportional to the integrated current flowing through the integration circuit, and the voltage control The oscillation means includes a voltage/current conversion means and a current controlled oscillation means, and the voltage/current conversion means includes a means for outputting a current signal that changes according to an input signal, and a means for outputting a current signal that changes according to an input signal, and a means for outputting a current signal that changes according to an input signal. means for changing the center level according to the output signal inputted from the compensation means, and the current controlled oscillation means changes the center level according to the output signal input from the compensation means.
4. The clock generating device according to claim 1, further comprising means for oscillating a signal having a frequency corresponding to a current signal inputted from the current converting means. 5. The current controlled oscillation means includes a multivibrator whose oscillation frequency is determined by the charging and discharging time of the capacitance, and means for controlling the charging and discharging current of the capacitance according to the output current signal of the voltage-current converting means. 5. The clock generating device according to claim 4, further comprising: 6. The multivibrator has two sets of switching circuits in which a load element made of MOS is connected to the collector of a switching element made of a bipolar transistor, and the input and output terminals of each switching circuit are cross-connected via a level shift circuit. and an emitter-coupled multivibrator configured by coupling the emitters of the switching elements with capacitance.
The clock generator described. 7. The switching circuit of the multivibrator is characterized in that the impedance of the load element is increased when the switching element is on, and the impedance of the load element is decreased when the switching element is off. The clock generating device according to claim 6. 8. The multivibrator is incorporated into a semiconductor device, and the capacitance forming the multivibrator connects two capacitances of the same structure and the same capacity formed in the semiconductor device to corresponding terminals. Claims 5 and 6, characterized in that they are connected in antiparallel to each other.
7. The clock generation device according to any one of 7. 9. The two capacitances are formed from first, second, and third conductors laminated with a dielectric interposed therebetween, and the first and third conductors are connected in common and connected in parallel. 9. The clock generating device according to claim 8. 10. The voltage controlled oscillation means and the compensation means are integrated into the same semiconductor device, and a capacitance forming the multivibrator and a capacitance forming an integrating circuit of the compensation means, 7. The clock generating device according to claim 5, wherein the clock generating device is formed to have the same structure. 11. The frequency/current conversion means includes an integrating circuit that is set and reset by the timing signal, a comparator that compares the output voltage of the integrating circuit with a predetermined reference voltage, and a charge that is driven by the output signal of the comparator. A pump circuit, a capacitance charged and discharged by the charge pump circuit, a low-pass filter that smoothes and outputs the terminal voltage of the capacitance, and a voltage/current that converts the output voltage of the low-pass filter into a current signal. a conversion circuit, an integral current control circuit that controls the integrated current of the integrating circuit according to the level of the converted current signal, and an output circuit that outputs a current signal according to the level of the converted current signal. A clock generating device according to any one of claims 4, 5, and 6, comprising: 12. A plurality of information processing devices are connected via a bus, each information processing device has means for generating a clock signal synchronized with a commonly given timing signal, and based on the clock signal, other information processing devices In an information processing system configured to synchronize and execute processing including data transfer between two signals, a clock signal generating means provided in each information processing device outputs a signal according to a phase difference between two signals. means, voltage controlled oscillation means for generating a signal with a frequency corresponding to the output signal of the phase comparison means, the timing signal being input, and the oscillation frequency of the voltage controlled oscillation means being responsive to changes in the frequency of the timing signal; and a compensation means for changing the range of the voltage controlled oscillation means, and the clock signal output from the voltage controlled oscillation means and the timing signal given from the outside are input to the phase comparison means. processing system. 13. A plurality of information processing devices are connected via a bus, and each information processing device has means for generating a clock signal synchronized with a commonly given timing signal, and based on the clock signal, other information processing devices In an information processing system configured to synchronize and execute processing including data transfer between two signals, a clock signal generating means provided in each information processing device outputs a signal according to a phase difference between two signals. voltage-controlled oscillation means for generating a signal with a frequency corresponding to the output signal of the phase comparison means; distribution means for converting and distributing the clock signal based on the output signal of the oscillation means; and compensation means for changing the oscillation frequency range of the voltage controlled oscillation means according to a change in the frequency of the timing signal, the clock signal output from the distribution means and the timing signal given from the outside. An information processing system characterized in that the information processing system is formed by inputting the following information into the phase comparison means. 14. A current source and a current from the current source flowing to two terminals 2
1. A charge pump circuit comprising: two current switches, the two current switches are operated differentially, and one of the two terminals is used as an output. 15. It has two sets of switching circuits in which a load element made of MOS is connected to the collector of a switching element made of a bipolar transistor, and the input and output terminals of each switching circuit are cross-connected via a level shift circuit, and the switching element An emitter-coupled multivibrator with two emitters coupled by capacitance. 16. The emitter-coupled type according to claim 15, characterized in that the impedance of the load element is increased when the switching element is on, and the impedance of the load element is decreased when the switching element is off. multi-vibrator. 17. The multivibrator is incorporated into a semiconductor device, and the capacitance forming the multivibrator connects two capacitances of the same structure and the same capacity formed in the semiconductor device to corresponding terminals. 17. The emitter-coupled multivibrator according to claim 16, wherein the emitter-coupled multivibrator is connected in antiparallel to each other. 18. The two capacitances are formed from first, second, and third conductors stacked with a dielectric interposed therebetween, and the first and third
18. The emitter-coupled multivibrator according to claim 17, wherein the conductors are commonly connected and connected in parallel. 19. An integrating circuit that is set and reset depending on the level of the input signal, a bias circuit that outputs a reference voltage, a comparator circuit that compares the output voltage of the integrating circuit and the bias voltage, and an output signal of the comparator circuit. A charge pump circuit is driven, a capacitance is charged and discharged by the charge pump circuit, a low-pass filter circuit smoothes and outputs the terminal voltage of the capacitance, and the output voltage of the low-pass filter circuit is converted into a current. Voltage to convert
a current conversion means; an integral current control means for controlling the integral current of the integrating circuit with the output current of the voltage/current conversion means;
1. A frequency-current conversion circuit, comprising: a frequency-current conversion circuit configured to output a current signal according to the level of the converted current signal.