JPH02234246A - Controlling system for cache coincidence process - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity by preparing the address array parts to store collectively the copies of address arrays of both instruction cache and operand cache parts and adding a coincidence process control part in common to both address array parts. CONSTITUTION:The address array parts 12 and 22 hold correctively the addresses of both an instruction cache 1 and an operand cache 2. Then a coincidence process control means 3 is added in common to both caches 1 and 2 to check in response to a coincidence process request whether the desired addresses are stored in the parts 12 and 22 or not and to perform a coincidence process if those addresses are stored in both parts 12 and 22. As a result, the hardware quantity can be reduced.

Description

Detailed Description of the Invention Technical Field The present invention relates to a cache matching processing control system, and particularly to an information processing apparatus having a cache storage device for storing a copy of a part of main storage record + TAIrrt information.
This paper relates to a cache consistency processing control system for maintaining consistency between data in main storage and data in cache storage. A block diagram of such a conventional cache matching processing control system is shown in Figure 2. The instruction fetching cache unit 1 holds instruction data, and includes a buffer register 11 for synchronization and an address array 1 indicating the location of the data.
2 and a data array 13 for holding instructions. Also, another address array 32 that holds a copy of the address array 12 necessary for matching processing, a buffer register 31a for synchronization, and this buffer register 3
Address array 3 with address 1a and this address
2, and a buffer register 36 for storing the comparison results. The operand retrieval cache unit 2 holds operand data, and the buffer register 2 for synchronization.
1, an address array 22 that indicates the location of data, and a data array 23 that holds operands. t
In addition, another address array 33 that holds a copy of the address array 22 necessary for matching processing, a buffer register 3lb for synchronization, and this buffer register 3lb
This includes a comparison circuit 35 that compares the address read from the address array 33 with this address, and a buffer register 37 that stores the comparison result. The match processing request address buffer unit 6 includes a buffer register 61 for synchronization, and a match register 61 for temporarily holding the matching processing request until that request is processed when there is a preceding match processing request. It has a processing buffer 62. The match processing request control circuit F#17 controls the match processing request address buffer section 6, as well as the instruction cache control circuit 8 and operand cache control circuit 9. In such a process, when a request is sent to the request address pool with a control signal, first, if there is no preceding matching processing request temporarily stored in the matching processing buffer 62, the request address is sent to the request address pool for instruction retrieval. The request is sent to the cache unit 1 and the instruction cache control circuit 8, and further to the operand retrieval cache unit 2 and the operand cache control circuit. As a result, matching processing is performed individually in each of the instruction cache section and operand cache section. In such a conventional match processing control system, in response to a match processing request, a request is sent to two separate cache units 1 and 2, an instruction cache and an operand cache, and each control circuit 8.9 and address Since it is an ellipse in which matching is performed by caching copies of
This requires two circuits with exactly the same control logic, which increases the amount of hardware used and causes an increase in costs. The purpose of this invention is: The purpose of this invention is to provide a cache matching processing control system that suppresses increases in hardware costs and reduces costs. According to the present invention, a main memory device, an instruction cache and an operand cache that store a copy of a part of the memory contents of the main memory device, and a main memory device, an instruction cache, and an operand cache that store a copy of a part of the memory contents of the main memory device. A cache matching processing control system for an information processing device, comprising a matching processing control means for maintaining consistency of information between the instruction cache and the operand cache, the system comprising an address array that collectively holds addresses of both the instruction cache and the operand cache. , a matching processing control means for detecting whether or not the requested address is stored in the address array in response to the matching processing request, and performing matching processing if the address is stored in the instruction cache and the matching processing request; A cache matching processing control system is obtained, which is characterized by providing a common feature for operand caches. Next, embodiments of the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.

1 is a cache section for fetching instructions and holds instructions. 11 is a buffer register for synchronization, 12 is an address array that indicates the location of data, and 13 is a data array that holds instructions. 2 is a cache section for fetching operands, which holds operands.
21 is a buffer register for synchronization, 22 is an address array that indicates the location of the operand, and 23 is a data array that holds the operand. Reference numeral 3 denotes a matching processing control unit that checks matching processing.

31 is a buffer register for synchronization, 32 is a copy of the instruction cache address array 12, and 33
is a copy of the address array 22 of the operand cache, and 234 and 35 are comparison circuits that check whether the address requested for matching processing exists in the cache. Reference numerals 36 and 37 are buffer registers for synchronization, and 4 is a control circuit that performs control for checking matching processing. 5 is a control circuit for controlling sending of a matching request to the matching processing check section when the matching request is sent. 6 is a buffer section for the match processing request address. Reference numeral 61 is a buffer register for synchronization, and reference numeral 62 is a buffer for temporarily holding data until the preceding matching processing request is processed. Next, we will explain the operation of each part. First, when a matching processing request address is sent, it is written to the matching processing buffer 62 via the buffer register 61. At the same time, if a matching processing control signal is sent to the control circuit 2 and processing is being performed by the matching processing control unit 3 due to a preceding matching processing request,
The match processing address is stored in the match processing buffer 62 and the next match request is accepted. If the preceding process has not been performed, the address is sent to the matching process control unit 3. This series of operations is controlled by the control circuit (■) 5. Next, it is determined whether there is a corresponding address in the copy 32 of the address array 12 of the instruction cache or the copy 33 of the address array 22 of the operand cache at the comparison time t? 434.35 and the result is sent to register 36.37. If the corresponding address does not exist, the next match processing request is accepted, and if the corresponding address does exist, a match processing signal is sent from the register 36.37, and the valid bit of the corresponding address in the copy 32.33 of the address array is set. To disable. A series of these controls is performed by control circuit (■) 4. When a match processing signal is sent to the instruction cache unit 1 or the operand cache unit 2, the register 1l or 2
By the address sent to 1, the valid bit of the corresponding address becomes valid, and one step of the matching process ends. As described above, according to the present invention, there is provided an address array section that collectively stores copies of both the address arrays of the instruction cache section and the operand cache section, and the address array section that is common to this collective address array section is provided. By providing a matching processing control section in the hardware, the double load of matching processing control can be halved. This has the effect of making it possible to reduce

[Brief explanation of the drawing]

FIG. 1 is a system block diagram of an embodiment of the present invention, and FIG. 2 is a system block diagram showing a conventional technique. Explanation of codes of main parts 1...Instruction retrieval cache 2...
Operand retrieval cache 3... Coincidence processing control unit 4.5... Control circuit Applicant: NEC Corporation (1 other person)

Claims (1)

[Claims] (1) Check the consistency of information between the main storage device, the instruction cache and operand cache that store copies of part of the memory contents of this main storage device, and the main storage device and the instruction cache and operand cache. A cache matching processing control system for an information processing device, the cache matching processing control system for an information processing device having a matching processing control means for maintaining a matching process, wherein an address array is provided for collectively holding addresses of both the instruction cache and the operand cache, and ,
The instruction cache and the operand cache are provided with a match processing control means that detects whether or not a requested address is stored in the address array and performs match processing if the address is stored. Cache matching processing control system.