JPH02235027A - Active matrix array substrate and production thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to display devices used in liquid crystal televisions for displaying images, displays for computer terminals, etc., and particularly relates to an active matrix array substrate used therein and a method for manufacturing the same. be.

Hereinafter, as a representative example, a description will be given focusing on those used in liquid crystal display devices.

Conventional technology In recent years, active matrix array substrates, in which switching elements such as thin film transistors (hereinafter referred to as TPT) and pixel electrodes are formed in a matrix on a light-transmitting substrate, have been actively developed mainly for application to display devices. It is. The structure of such an active matrix array substrate will be explained using FIG. 8. 1 is a TPT whose constituent elements are polycrystalline silicon or non-quality silicon formed on a transparent substrate (not shown). A liquid crystal display 2 is constructed by injecting liquid crystal 5 between a pixel electrode 3 electrically connected to the drain electrode of the TFT 1 and a transparent counter electrode 4 on a transparent substrate forming a color filter.

In addition to the capacitance caused by the liquid crystal 5, additional capacitance formed on the active matrix array substrate may be added. 7 is a gate wiring (or generally referred to as a row wiring) connected to the gate electrode of the TFTI, and 8 is a source wiring (or generally referred to as a column wiring) connected to the source electrode of the TFTI. 9 and 10 are peripheral drive circuits. In this figure, the parts other than the peripheral drive circuits 9 and 10, the liquid crystal 5, and the counter electrode 4 are constructed on one substrate as an active matrix array substrate.

In order to manufacture the above active matrix array substrate, a photolithography process using a photomask is required multiple times. Active matrix array base for display devices. In the case of plates, fine processing is required, so
Ancillary equipment such as an exposure machine and a positioning mechanism (mask alignment mechanism) that have the same level of performance as those for semiconductor processes are used. Therefore, the more times a photolithography process using a photomask is performed, the more times a high-performance and expensive exposure machine must be used, which increases the manufacturing cost of the active matrix array substrate. Furthermore, defects such as alignment defects occur due to the photolithography process, and the yield decreases as the number of photolithography processes increases.

From this point of view, efforts have been made to reduce the number of times a photomask is used as much as possible.

The first conventional example shown in FIG. 9 is a plan view of the main part of an active matrix array substrate manufactured using only two photomasks, and shows one pixel electrode and its surroundings. ing. 8a18b is a source wiring, 3 is a pixel electrode, and 7as7b is a gate wiring. 10th
The figure is a sectional view taken along the CD line in FIG. 9. The manufacturing method is to form a transparent conductive film 12 and a low-resistance semiconductor layer 13 on a transparent substrate 11, and then form a pattern using a first photomask to form a pattern between the source wiring 8 al 8 b and the pixel. The electrode 3 and the drain electrode 3a connected to the pixel electrode 3 are formed at the same time. Thereafter, a semiconductor layer 14, a gate insulating film 15, and a gate electrode material are deposited, and these three layers are patterned into a gate wiring 7a using a second photomask. At this time, the low resistance semiconductor layer 13 other than the gate wiring portion is also removed. 1 is a thin film transistor (TPT)
), and the signal transmitted to the pixel electrode 3 is transmitted between the source wiring 8a and the drain electrode 3a (for example, the above structure is described in Japanese Patent Publication No. 59-501
582).

When an active matrix array substrate is manufactured by minimizing the number of times a photomask is used as in the first conventional example, the semiconductor layer 14 of the switching element is often formed in the same pattern shape as the gate wiring 7a.

Therefore, adjacent switching elements are connected to each other by the semiconductor layer 14. When the elements are connected by the semiconductor layer 14, there is a drawback that unnecessary signals flow in from adjacent elements (wirings) and the quality of the signals transmitted to the pixel electrodes 3 is significantly degraded. For example, in FIG. 10, in addition to the original signal from the source line 8a, a signal from the source line 8b of the adjacent TFT 1 is also transmitted to the drain electrode 3a.

In other words, the problem is that the parasitic TPT exists in the region indicated by 1'.

Of course, by increasing the number of photomasks used and using a photolithography process, signals from adjacent elements can be separated (element m
), but for the reasons mentioned above, there is a strong need for an element isolation technique that does not increase the number of times a photomask is used.

Conventionally, as a method for this purpose, as in the second conventional example shown in FIG.
A method has been proposed in which the device is installed between the
EEDINGS of the CONFERENCE
; EURODISPLAY '87) [: September 1987, Londonco, P. 180). Figure 12 is the first
2 is a cross-sectional view taken along the EF line in FIG. 1. FIG.

In this case, the inflow of signals from the source wiring 8b due to the parasitic TFTI is suppressed by the function of the source electrode 8C.

Problems to be Solved by the Invention However, the configuration of the second conventional example causes some practical problems.

In other words, since the element size of TPT increases, TPT
The parasitic capacitance (between gate and drain) increases. When an image is displayed with this configuration, there is a drawback that the switching noise becomes thicker due to the coupling of the capacitive components (for this phenomenon, see, for example, IEICE Technical Report Vol. 88 No. 350 EID 88-59). :
(corresponds to Δv1 in the reference document).

In particular, switching noise causes DC components to be generated in the liquid crystal display, and in the case of liquid crystal displays that require accurate AC drive, it not only deteriorates the image quality (for example, causing severe image burn-in), but also , issues also arise in terms of ensuring reliability (life).

Alternatively, as can be seen by comparing with the first conventional example (see Fig. 9), as the TPT becomes larger, the area of the pixel electrode becomes smaller, resulting in a disadvantage that the aperture ratio (effective display area) becomes smaller. .

In view of the above problems, an object of the present invention is to provide an active matrix array substrate and a method for manufacturing the same, which can perform element isolation with small parasitic capacitance without increasing the number of photolithography steps using photomasks. purpose.

Means for Solving the Problems The means of the present invention for solving the above problems are as follows.

That is, in the active matrix array substrate according to claim 1, in a configuration in which adjacent switching elements electrically connected to the same row wiring are connected by a semiconductor layer, a branch point A is provided in the row wiring, and a branch point A is provided from the branch point A. A branch line Xb connected to the pixel electrode of the row line is installed, a point where the column line or the branch line Yb connected to the column line intersects the branch line Xb is defined as an intersection B, and switching is performed using the intersection B. The element is installed, and the intersection 4B is installed between the pixel electrode and the branch point A. With this configuration, there is always an intersection B in the inflow path of unnecessary signals from adjacent elements (wirings) via the semiconductor layer, and most of the unnecessary signals flow through the intersection B before flowing into the channel section of the switching element. flows into.

Alternatively, in the method for manufacturing an active matrix array substrate according to claim 4, a gate wiring (row wiring) made of a non-transparent material having a slit in a part of the wiring is formed on a transparent substrate.
and then depositing a gate insulator layer and a semiconductor layer,
Then, with a positive photoresist coated on the semiconductor layer, the photoresist is exposed to light without a photomask by irradiating light from the back side of the substrate, and after development, the semiconductor layer is etched using this resist. At this time, an active matrix array substrate is created by overexposure to make the resist pattern thinner than the gate wiring pattern, or by over-etching, or both, so that no semiconductor layer remains on the gate wiring in the slit portion. . This method separates the semiconductor circuitry that connects the elements into individual elements. Furthermore, in the method for manufacturing an active matrix array substrate according to claim 5, a gate wiring (row wiring) made of a non-transparent material having a slit in a part of the wiring is formed on a transparent substrate, and then A gate insulator layer is applied, and a negative photoresist is applied on the gate insulator layer, and the photoresist is exposed to light without a photomask by irradiating light from the back side of the substrate, and then developed. A semiconductor layer is deposited on the insulator layer, and unnecessary portions of the semiconductor layer are removed by lifting off the photoresist. At this time, the photoresist is overexposed to lift off the semiconductor layer on the gate wiring in the slit portion, thereby creating an active matrix array substrate. With this method, the semiconductor layer that connects the elements is separated for each element.

Function: With the above-described configuration, the present invention makes it possible to perform element isolation with small parasitic capacitance without increasing the photolithography process using a photomask.
Even in the case of exposure from the back side of the substrate, a photomask is not required and a very inexpensive exposure machine that does not require an alignment function etc. can be used). Therefore, the inflow of unnecessary signals from adjacent TPTs is reduced, and the quality of signals transmitted to the pixel electrodes is improved. If a liquid crystal display is performed using the active matrix array substrate of the present invention, display quality comparable to that obtained by separating elements using a photomask can be ensured.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view of the main parts of the active matrix array substrate in the first embodiment of the present invention, showing one pixel electrode 3 and its surroundings (the first embodiment shown in FIG. 9). Components that have the same purpose as the conventional example are given the same reference numerals.) 8a1 and 8b are source wirings, 3 is a pixel electrode,
7al7b is a gate wiring. Gate marking 7at7b
A branch point A is provided for each TFT, and a branch line Xb is provided from the branch point A. Similarly, source wiring 8 aN8
A branch line Yb is provided from b, and these two branch lines X
b and Yb intersect at intersection B.

A portion 1 from the intersection B to the pixel electrode 3 constitutes the TPT.

FIG. 2 is a sectional view taken along the line GH in FIG. 1.

In terms of process, this example uses the same process as the conventional example. That is, after forming a transparent conductive film (ITO) 12 and a low resistance semiconductor layer (n'-amorphous silicon) 13 on a transparent substrate (glass) 11, a pattern is formed using a first photomask. The source wiring 8a and the branch wiring Yb are formed.
and the pixel electrode 3 are formed at the same time. After this, a semiconductor layer (non-quality silicon) 14 and a gate insulating film (silicon nitride) 1
5 and a gate electrode material (metal thin film) are deposited, and these three layers are patterned into the shapes of gate wiring 7a and branch wiring Xb using a second photomask. At this time, the low-resistance semiconductor layer 13 other than the gate wiring portion is also removed. 1 is a region constituting a thin film transistor (TPT).

When an active matrix array substrate was created with the configuration of this example and a liquid crystal display was performed using it, the inflow of unnecessary signals from adjacent elements (wirings) was suppressed to a minimum, and it was possible to suppress the inflow of unnecessary signals from adjacent elements (wirings). Achieved image quality comparable to those with separate elements.

Furthermore, compared to the second conventional example shown in Fig. 11, it was confirmed that not only could the aperture ratio be increased, but also the switching noise (throughput) caused by the parasitic capacitance of the TFT could be reduced. .

In the configuration of this embodiment, unnecessary signals from adjacent elements (wirings) flow in through the branch point A, but before reaching the pixel electrode 3, the unnecessary signals reach the branch i! a, ii
Since it flows into Yb (intersection B), the amount flowing into the pixel electrode 3 becomes extremely small, and it is considered that element isolation with a performance sufficient for practical use is realized. Compared to the second conventional example, not only is the switching noise small, but the conventional example is equally affected by adjacent pixels on the left and right, whereas this example eliminates unnecessary signals from the adjacent pixels on the left. The inflow path intersects twice with the source wiring 8a and the branch wiring Yb, which are at the same potential, and it is considered that the state of element isolation is better.

FIG. 3 is a plan view of the main parts of the active matrix array substrate in the second embodiment of the present invention, showing one pixel electrode 3 and its surroundings (the first pixel electrode 3 shown in FIG. 9). Components that have the same purpose as the conventional example are given the same reference numerals.) 8ax8b is a source wiring, 3 is a pixel electrode, 7
a1 7b is a gate wiring. Gate wiring 7a1 7
In b, a branch point A is provided for each TFT, and a branch line Xb is provided from the branch point A. In this embodiment, the pixel electrode 3 is arranged in a delta (triangular) arrangement, so the source marking 8
No branch wiring Yb is provided in a1 8b. The branch line Xb and the source line 8a intersect at an intersection B.

A portion 1 from the intersection B to the pixel electrode 8 constitutes the TPT.

FIGS. 4(a) to 4(C) are process cross-sectional views along the line IJ in FIG. 3. In terms of process, this example uses a process different from the conventional example (method by the inventors of the present invention,
For example, Japanese Patent Application No. 83-97008 is applied). A metal Cr thin film is deposited on a transparent substrate 11, and a gate wiring 7a is patterned using a first photomask.

Thereon, a gate insulating film (silicon nitride) 15, a semiconductor layer (amorphous silicon) 14, and a low resistance semiconductor layer (n◆-amorphous silicon) 13 were successively formed. In this state, a positive photoresist is applied and exposed by irradiating ultraviolet light from the back side of the substrate as shown in Figure 4 (a) (a photomask is not required and can be carried out with an inexpensive exposure device). . After developing the photoresist, the low resistance semiconductor layer 13 and the semiconductor layer 14 are etched (FIG. 4(b)). Thereafter, the resist is removed, a transparent conductive film is formed, and a pattern is formed using a second photomask to simultaneously form the source wiring 8a and the pixel electrode 3. At this time, portions of the low-resistance semiconductor layer 13 other than the second photomask pattern are also removed. 1 is a region constituting a thin film transistor (TPT) (FIG. 4(C)).

Note that a photomask is not particularly required during etching to take out the gate wirings 7a1 and 7b to the outside.
Even with this configuration, the photolithography process using a photomask is carried out twice (the alignment between patterns only needs to be done once).
The active matrix array substrate is completed.

When an active matrix array substrate was created with the configuration of this example and a liquid crystal display was performed using it, the inflow of unnecessary signals from adjacent elements (wirings) was suppressed to a minimum, and it was possible to suppress the inflow of unnecessary signals from adjacent elements (wirings). Achieved image quality comparable to those with separate elements.

FIG. 5 is a plan view of the main parts of the active matrix array substrate in the third embodiment of the present invention, showing one pixel electrode 3 and its surroundings (the first pixel electrode 3 shown in FIG. 9). Components that have the same purpose as the conventional example are given the same reference numerals.) 8 aN 8 b is a source wiring, 3 is a pixel electrode, and 7 a1 7 b is a gate wiring. Gate wiring?
a) A slit 19 is provided in 7b.

1 is the TPT part. FIGS. 6(a) to 6(C) are process cross-sectional views taken along the line KL in FIG. 5. In terms of process, this embodiment uses almost the same process as the second embodiment.

Gate wiring 7 made of metal Cr thin film on transparent substrate 11
A is patterned using a first photomask, and a gate insulating film (silicon nitride) 15 and a semiconductor layer (
Amorphous silicon) 14 and a low-resistance semiconductor layer (n◆-amorphous silicon) 13 were successively formed. In this state, a positive photoresist is applied, irradiated with ultraviolet light from the back side of the substrate, and developed (no photomask required). At this time, overexposure is performed to make the resist pattern 18 thinner than the gate wiring 7a by di (FIG. 6(a)). Furthermore, using this resist, a low resistance semiconductor layer 13 and a semiconductor layer 1 are formed.
4 and etched. At this time, over-etching is performed to make the etching pattern thinner than the resist pattern 18 by d2. Clouding due to over-exposure and over-etching (dl+d2) The semiconductor layer 14 does not remain on the gate wiring 7a in the area where the slit 19 is located (FIG. 6(b)). The resist is removed, a transparent conductive film is formed, and a pattern is formed using a second photomask to simultaneously form the source wiring 8a and the pixel electrode 3. At this time, portions of the low-resistance semiconductor layer 13 other than the second photomask pattern are also removed. 1 is a region constituting a thin film transistor (TPT) (FIG. 6(C)). As shown in FIG. 5, in this embodiment, the semiconductor layer 14 is completely separated between adjacent devices. Note that a photomask is not particularly required during etching for external extraction of the gate wirings 7a1 and 7b, so even with this configuration, the photolithography process using a photomask is performed twice (the alignment between patterns only needs to be done once), and the active matrix is completed. The array board is completed.

If an active matrix array substrate is created with the configuration of this example and a liquid crystal display is performed using it, adjacent elements (
This suppresses the inflow of unnecessary signals from (wires) and achieves image quality comparable to that of conventional photomasks that separate elements.

7(a) to (c) are process cross-sectional views of the main parts of the active matrix array substrate in the fourth embodiment of the present invention (the element layout is the same as the third embodiment, so it is omitted) 7(a) to 7(C) correspond to process cross-sectional views along the line KL in FIG. 5. Components having the same purpose as the third embodiment are designated by the same reference numerals). A gate wiring 7a made of a metal Cr thin film was patterned on a transparent substrate 11 using a first photomask, and a gate insulating film (silicon nitride) 15 was formed thereon.

In this state, a negative photoresist is applied, irradiated with ultraviolet light from the back side of the substrate, and developed (no photomask required). At this time, overexposure is performed to make the resist pattern 20 thicker by d3 than the gate wiring 7a. Due to this overexposure, the gate wiring 7a in the part where the slit 18 is located
A resist remains on top (FIG. 7(a)). Furthermore, a semiconductor layer (amorphous silicon) 14 and a low resistance semiconductor layer (n''-amorphous silicon) 13 are successively formed on this resist (FIG. 7(b)). The low-resistance semiconductor JI 13 and the semiconductor layer 14 on the resist are removed by lift-off.Due to overexposure d3, the semiconductor layer 14 does not remain on the gate wiring 7a in a certain part of the slit 19.After this, a transparent conductive film is removed. A pattern is formed using a second photomask, and the source wiring 8a and the pixel electrode 3 are simultaneously formed.At this time, the low resistance semiconductor layer 13 is also removed from the portions other than the second photomask pattern.

1 is a region constituting a thin film transistor (TPT) (FIG. 7(C)). Similar to the third embodiment, the semiconductor layer 14 is completely separated between adjacent devices.

Note that a photomask is not particularly required during etching to take out the gate wirings 7a1 and 7b to the outside.
Even with this configuration, the photolithography process using a photomask is carried out twice (the alignment between patterns only needs to be done once).
The active matrix array substrate is completed.

If an active matrix array substrate is created with the configuration of this example and a liquid crystal display is performed using it, adjacent elements (
This suppresses the inflow of unnecessary signals from (wires) and achieves image quality comparable to that of conventional photomasks that separate elements.

Furthermore, as shown in the conventional example, a staggered TFT using two photomasks was reported as having the lowest number of photomasks in the past, but in this conventional structure, the number of photomasks from the glass substrate side The photoconversion caused by the incident light was large, and some kind of light shielding was required.
The TFT 1 of this embodiment (the same applies to the second and third embodiments) is an inverted staggered TFT, and has the excellent effect of suppressing photoconversion because the gate electrode functions as a light shield. In addition to this, the gate wiring 7 aN 7 b in the TFT section is completely covered with the gate insulating film 15, which reduces interface leakage and has an advantageous configuration in terms of image quality and reliability. .

Effects of the Invention According to the active matrix array substrate or the method for manufacturing an active matrix array substrate of the present invention, as shown in the embodiments above, a high-performance active matrix array substrate with low parasitic capacitance and high element isolation can be obtained. can be provided without increasing the photolithography process using a photomask. Therefore, it is possible to minimize the number of times an expensive exposure machine used in the photo-injector lithography process using a photomask is used, and the high cost, which is a major drawback of active matrix array substrates, can be suppressed. Furthermore, the occurrence of defects associated with the photolithography process, such as alignment defects, is theoretically reduced, and the practical effect is extremely large.

[Brief explanation of drawings]

FIG. 1 is a plan view of the main parts of an active matrix array substrate according to the first embodiment of the present invention, and FIG.
-H sectional view, FIG. 3 is a plan view of the main part of an active matrix array substrate in the second embodiment of the present invention, and FIGS. 4(a) to (C) are I in FIG. 3 showing the manufacturing process. -J sectional view, FIG. 5 is a plan view of the main part of the active matrix array substrate in the third embodiment of the present invention, and FIG. 6(a)
~(C) is a sectional view taken along line K-L in FIG. 5 showing the manufacturing process;
7(a) to (C) are process sectional views of main parts of an active matrix array substrate in a fourth embodiment of the present invention,
8 is a circuit diagram of an active matrix array substrate and a main part of a liquid crystal display device using the same, FIG. 9 is a plan view of a main part of an active matrix array substrate in the first conventional example, and FIG. 11 is a sectional view taken along line C-D in the figure.
FIG. 12 is a plan view of a main part of an active matrix array substrate in the conventional example, and FIG. 12 is a sectional view taken along the line EF in FIG. 1●●●Thin film transistor (TFT), 3●●●pixel electrode, 7a+7be●●gate wiring (row wiring), 8a, 8
b●●●source wiring (listed lines), 11●●●board, 1
4●Fist●Semiconductor layer, 15Fist●●Gate insulating film, 18.
18●●●Body type resist, 19●Fist●Slit, 20
●●●Negative resist, A●●● branch point, B●●● intersection, Xb, Yb@●● branch wiring. Name of agent: Patent attorney Shigetaka Awano Haka 1 contractor 1st figure 19-11

Claims (5)

[Claims] (1) Row wiring and column wiring are provided on an insulating substrate via an insulating layer, and a switching element is electrically connected to the row wiring and the column wiring, and a pixel electrode is connected to the switching element. In an active matrix array substrate having a matrix of the row wiring, a branching point A is provided in the row wiring, a branch wiring Xb is installed which is connected from the branching point A to the pixel electrode of the row wiring, and the column wiring or the column The point where the branch line Yb connected to the wiring and the branch line Xb intersect is defined as an intersection B, the switching element is installed using the intersection B, and the switching element is installed between the pixel electrode and the branch point A. An active matrix array substrate characterized in that an intersection B is provided. (2) The active matrix array substrate according to claim 1, wherein the switching elements are thin film transistors. (3) The active matrix array substrate according to claim 2, wherein the thin film transistor is made of non-single crystal silicon. (4) On a light-transmitting substrate, a gate wiring made of a non-light-transmitting material covering a specific area of the substrate surface, an insulating layer covering the exposed surface of the substrate surface and the gate wiring, and a gate wiring on the insulating layer In a method for manufacturing an active matrix array substrate having a semiconductor layer covering a specific region, and a switching element connected to a source electrode and a drain electrode of the semiconductor layer,
The step of forming the semiconductor layer includes a step of forming a gate wiring having a slit in a part of the wiring, a step of depositing a semiconductor layer on the insulating layer, and a step of depositing a positive photoresist on the semiconductor layer. It consists of a step of coating, a step of irradiating light from the back side of the substrate, a step of developing the photoresist, and a step of etching the semiconductor layer using the developed photoresist. Alternatively, a method for manufacturing an active matrix array substrate, characterized in that the semiconductor layer on the gate wiring in the slit portion is also etched by over-etching. (5) On a light-transmitting substrate, a gate wiring made of a non-light-transmitting material covering a specific area of the substrate surface, an insulating layer covering the exposed surface of the substrate surface and the gate wiring, and a gate wiring on the insulating layer In a method for manufacturing an active matrix array substrate having a semiconductor layer covering a specific region, and a switching element connected to a source electrode and a drain electrode of the semiconductor layer,
The step of forming the semiconductor layer includes a step of forming a gate wiring having a slit in a part of the wiring, a step of applying a negative photoresist on the insulating layer, and a step of irradiating light from the back side of the substrate. and developing the photoresist, depositing a semiconductor layer on the developed photoresist and the insulator layer, and lifting off the photoresist. A method for manufacturing an active matrix array substrate, characterized in that the semiconductor layer on the gate wiring in the slit portion is also lifted off by overexposure.