JPH02235155A - Data reading circuit - Google Patents

Abstract

PURPOSE:To speed up data reading by providing a data reading circuit with a control signal generating part, extending the period of an address by a 1st control signal to shift a phase and selecting data by a 2nd control signal. CONSTITUTION:Data with the same contents are written in n storage parts constituting a storage part 3 and a reading address having a 1/n period is inputted to a low speed address conversion means 2. The conversion means 2 extends the period of the reading address to n times by using the 1st control signal outputted from a control signal generating part 4 and shifts the phase by 1/n. The converted low speed reading addresses of n sequences are successively sent to the corresponding storage parts and the read data are applied to the selector 5. The 2nd control signal outputted from the generating part 4 is inputted to the selector 5 and the data corresponding to the reading addresses are successively selected and outputted. Thereby, the access time of the storage part 3 is turned to 1/n and the data reading speed is increased. Provided that n is an integer >=2.

Description

[Detailed Description of the Invention] [Summary] For example, with respect to a data reading circuit used in digital signal processing, the first applied Using control signals. The read address to be input has a period n times the period of the read address. It consists of a low-speed address conversion means that converts into n series of low-speed read addresses whose phases are shifted by (1/n) from each other and sequentially sends them out, and n memory parts in which the same data is written, and the low-speed read address a storage section (3) in which the corresponding data is read out from the storage section inputted by the user;
a selector whose operation is controlled so that data corresponding to input read addresses are sequentially sent out to the outside by a second control signal applied; the low-speed address conversion means; and a first control signal which controls the operation of the selector. and a control signal generating section that generates a control signal and a second control signal.

[Industrial application field]

The present invention relates to a data reading circuit used, for example, in digital signal processing.

The recent increase in the scale and speed of integrated circuits has enabled real-time processing of digital signal processing (DSP), and the use of digital signal processing is rapidly increasing in various fields.

Typically. The internal functions of DSP are program counter,
A program ROM (read only memory), a decoder section including a program decoder and a data ROM, a data RAM (random access memory), a data memory section including a register file, and a multiplier. It consists of an arithmetic unit including an accumulator, an input/output unit, etc.
In response to the increase in the speed of p, it is desired to increase the speed of reading data written in the storage unit.

[Conventional technology]

FIG. 4 is a block diagram of a conventional example, and FIG. 5 is an explanatory diagram of the operation of FIG. 4.

Here, the symbols on the left side of FIG. 5 indicate the waveforms of the portions with the same symbols in FIG. The operation shown in FIG. 4 will be explained below with reference to FIG.

As shown in Figure 5-■, read addresses 1, 2, 3, etc.
are added to the ROM 12 via the buffer 11, and the data written in the corresponding portions are sequentially read out (see FIG. 5--). Here, is T 1? This is the access time of the OM 12, which is the time from when the read address is input to the ROM until the write data is read.

[Problem to be solved by the invention]

Well, there are high speed and low speed ROMs, and high speed ROM
In this case, for example, the access time is several IQns or less. In the case of low-speed ROM, for example, several hundred ns
As described above, there is a problem in that it is difficult to read data in a time shorter than the access time determined using a low-speed ROM.

An object of the present invention is to speed up the reading of data written in a storage section.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 2 uses the first control signal to be applied to input a read address with a period n times the period of the read address, and whose phases are shifted by (1/n) from each other.
3 is a low-speed address conversion means that converts into a series of low-speed read addresses and sequentially sends them out, and 3 is composed of n storage parts in which the same data is written. This is a storage section from which corresponding data is read from a storage section to which the low-speed read address is input.

Further, 5 is a selector whose operation is controlled by a second control signal applied so that data corresponding to the input read address is sequentially sent out to the outside, and 4 is the low-speed address conversion means, the selector. This is a control signal generation section that generates a first control signal and a second control signal that control operations.

[Operation] According to the present invention, data having the same content is written into n storage portions constituting the storage section 3.

Next, when a read address having a cycle of (1/n) of the access time of the storage section is input to the low-speed address conversion means 2, this conversion means 2 uses the first control signal from the control signal generation section. The period of this read address is extended by n times, and the addresses are converted into n series of low-speed read addresses whose phases are shifted by (1/n) from each other and are sequentially sent to the corresponding storage portions.

Therefore, the corresponding data is read from the storage portion to which the low-speed read address has been added and is added to the selector 5. Since the second control signal from the control signal generator 4 is added here, the data corresponding to the input read address is sequentially read. Selected and output. In other words, the time from when a read address is input to when data is output is the sum of (1/n) of the access time of the storage section and the delay time at the low-speed address conversion means and selector. The speed of reading written data is increased.

〔Example〕

Figure 2 is a block diagram of an embodiment of the present invention. FIG. 3 shows an explanatory diagram of the operation of FIG. 2.

Note that the symbols on the left side of FIG. 3 are the waveforms of the parts with the same symbols in FIG. 2, and in FIG. 1■. ■、■ DI+
Dz... indicates data written to the portion corresponding to read address 1,2... In addition, the address holding section 2
1. 22 is a component of the address conversion means, #I RO
The M 3L #2 ROM 32 is a component of the storage section 3 . Hereinafter, the operation in FIG. 2 will be explained with reference to FIG. 3, assuming n=2.

First, as shown in FIG.
．． 22 at the same time.

On the other hand, two series of first control signals (hereinafter abbreviated as CKI.CK!) are sent from the control signal generating section 4 to the address holding section 21. It was sent out on the 23rd. This CKI. CKZ has a half-phase shift in phase with respect to each other. Both periods are twice the period of the read address, as shown in FIG.

, furthermore, CKI. The address holding unit writes the input read address in the L parts a and a' of CKz, holds it in the H parts b and b', and updates it to the next input read address in the next part c and c'. be done.

Therefore, as shown in FIG. 3-■, the address holding unit 21 is
Write the read address 1 shown in Figure 3 (1) in the section b, hold it in the section b, convert it to a low-speed read address 1 with a period twice the period of the read address, and write the read address 1 shown in Fig. 3.
Add to ROM 31. As a result, the corresponding data D is read out after the access time T, as shown in FIG. 3-1. Note that when read address 1 is input, the H portion of CK2 is added to the address holding section 22, so read address 1 cannot be written.

Next, when the read address 2 is input, the address holding unit 22 writes it in the a° part of FIG. Add. Therefore, the corresponding data D2 is read out after the access time T, as shown in FIG.

Thereafter, read addresses 3, 5.7 are stored in address holding unit 2.
1, 4, 6.8 are sequentially converted into corresponding low-speed read addresses in the address holding section 22, and data D3 to D08 are read out alternately from the corresponding ROM.

Now, as shown in Figure 3 - ■ and ■, #I ROM 3
1, #2 Two series of data read from the ROM 32 and having a half phase shift from each other are sequentially applied to the selector 5. Here, a second control signal is applied from the control signal generator 4 to control the selector so that the data corresponding to the read address is sent to the outside.
The data corresponding to the read addresses are sequentially sent out as shown in FIG.

In other words, from the point of view of input/output of the data readout circuit, RO
The output of the ROM is read every half of the access time of M, the holding time of the address holding section, and the delay time of the selector, which speeds up the reading of data written in the memory section. .

〔Effect of the invention〕

As described above in detail, the present invention has the effect of speeding up the reading of data written in the storage section.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, Fig. 4 is a block diagram of a conventional example, and Fig. 5 is a block diagram of an embodiment of the present invention. The operation explanatory diagram of FIG. 4 is shown. In the figure, 2 indicates a low-speed address conversion means, 2 indicates a storage section, 2 indicates a control signal generation section, and 2 indicates a selector. 34 2 Fig. 0 Vertical review of VSX

Claims (1)

[Claims] Using the first control signal to be applied, the input read address has a period n times the period of the read address (a positive integer of n≧2), and the phases are mutually (1 /n) Consists of a low-speed address conversion means (2) that converts into n series of low-speed read addresses that are shifted by phase and sequentially sends them out, and n storage parts in which the same data is written,
The storage unit (3) reads out the data corresponding to the memory portion to which the low-speed read address is input, and the data corresponding to the input read address is sequentially sent out to the outside by the applied second control signal. a selector (5) whose operation is controlled in a similar manner; and the low-speed address conversion means;
A data reading circuit comprising a control signal generating section (4) that generates a first control signal that controls the operation of a selector and a second control signal.