JPH02235291A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To attain furthermore rapid operation by driving address decoders and registers in parallel so that the address decoders fetch the succeeding addresses to start decoding operation. CONSTITUTION:Registers 32, 34 are also inserted between the decoders 12, 14 and a memory cell array 10 to execute the pipeline operation of a memory together with registers 22, 28. Registers 36, 38 are inserted after a data-in (Di) register 24 and a write enable (WE) register 26 so as to be matched with the pipeline operation and driven by a clock (CLK). In a write cycle, an address A is fetched to the register 22 and the data Di written by pipeline processing are sequentially written in a cell selected by the address A of a memory cell array. In a read cycle also, the storage data of the memory cell are sequentially read out. Consequently, a clock period can be shortened and a rapid memory can be obtained.

Description

[Detailed Description of the Invention] [Summary of the Invention] Regarding a synchronous semiconductor memory device that aims to shorten the access cycle, with the aim of further increasing the speed, an address decoder and a memory cell array of the synchronous semiconductor memory have been developed. A register is provided in between, and the address decoder decodes the address. Upon receiving the decoded output, the register selects the word line and bit line of the memory cell array. When the register makes the selection, the address decoder selects the next one. These address decoders and registers are configured to operate in parallel so as to take in an address and enter a decoding operation.

(Industrial Application Field) The present invention relates to a synchronous semiconductor memory device that aims to shorten the access cycle.In recent years, in response to the increase in speed of systems, there has been a demand for faster access speeds of the memory used. High-speed operation is generally addressed by miniaturizing the memory device itself.On the other hand, there is a method called synchronous memory (synchronous memory) that allows stable high-speed access.
Also called self-timed RAM. ) The present invention relates to this synchronous memory. [Prior Art] Figure 3 shows the general configuration of a conventional synchronous memory. 1
0 is a memory cell array, 12 is a row decoder, 14 is a column decoder, 16 is a sense amplifier and a write amplifier, and these parts 20 are the same as an asynchronous memory. The synchronous type differs in that it is provided with registers 22, 24, 26, and 28 and a pulse generation circuit 18, and is operated by a clock CLK. In other words, in the asynchronous type, taking reading as an example, an address is given to a decoder, a word line and a bit line are selected by the decode output, and data stored in a memory cell at the intersection of these selected word lines and bit lines is retrieved. ．． During this time, there is no clock or the like that regulates the timing of the operation, and only the data that is read by giving the address is retrieved. On the other hand, in the synchronous type, the operation timing is specified by giving a cloth. Again, taking reading as an example, address 8 is given, this is taken into the register 22 using the clock CLK, and the row/column decoder, memory cell array, and sense amplifier are sequentially operated. Next clock CL
At K, the sense amplifier output is taken into the register 28, and the next address A is taken into the register 22 to perform the next access operation. Thereafter, this is repeated, and each time the clock CLK is applied, the access operation is started and the previous access result is retrieved (read data DO is output). [Problems to be Solved by the Invention] As described above, in a synchronous memory, the period of the clock CLK determines the access cycle. In terms of a read cycle, the clock cycle is determined by the time it takes to decode an address, select a memory cell array, and generate an output in the sense amplifier. For example, the time to decode is 3 nS, and the time to operate the cell array is 5 nS. , If the operating time of the sense amplifier is 2nS, the total is 10nS, which is the minimum period, and in terms of clock frequency it is 10nS.
0MH2 is the highest frequency.

Synchronization of memory is one method for achieving high-speed operation, but the conventional method has the above-mentioned upper limit.

Yoshiaki's objective is to improve this and further speed up the process. [Means for Solving the Problems] As shown in Figure 1, in the present invention, a register is also inserted between the decoder and the memory cell array. 32 and 34 are these registers, 32 is provided between the row decoder 12 and the memory cell array 10, and 34 is provided between the column decoder 14 and the memory cell array 10. These registers 32.34 are provided to register 22.34.
28 to operate the memory in a pipeline. Registers 36 and 38 are the register 24 for data in D1 and the write enable WE in order to match this pipeline operation.
This is a register inserted after the register 26 for . These registers are operated by clock CLK.

[For production]

In this synchronous memory, in a write cycle, ① capture address A to register 22, start decoding, capture write data D1 to register 24, capture write enable WE26 to register 26, ① register 32.34 of decoding result. , accessing the memory cell array, loading the contents of registers 24 and 26 into registers 36 and 38, supplying write data Di to the write amplifier, writing enable of the cell array, and writing data are performed every clock CLK. , write data DI is sequentially written to cells selected by address A of the memory cell array by pipeline processing. Also, in the read cycle, address A to register 22 is
Taking in, start decoding, write enable WE to register 26 (currently the H/L level is reversed and specifies read), ■ taking in decode output to registers 32 and 34, accessing memory cell array, register 3 Taking in the contents of the register 26 and setting the cell array mode to register 28 Taking in the sense amplifier output into the register 28 is performed every clock CLK, and the data stored in the memory cell selected at address A is processed by pipeline processing. are read out sequentially. What is carried out in each clock cycle is: ■ Loading the address into the register 22, starting decoding, ■ Loading the decoding result into the registers 32 and 34, and cell access. Since this is not done in one clock cycle, it is possible to shorten the clock cycle and therefore realize a high-speed memory. However, the first data read (or the time from when the address is given until the read data comes out) is 2
After a clock cycle, this is actually slower than before (because of the additional registers). However, since the amount of processing in each clock cycle is reduced, the clock frequency can be increased, and the overall speed can be increased. Figure 2 shows a time chart of write and read operations. For writing, address A to register 22.24,
The write data Di is taken in at every rising edge of each clock, and with a delay of one clock, data writing into the data fetching cell array of the registers 32 and 34 is carried out at every rising edge of each clock. In the read operation, the address A is taken into the register 22 and decoding is started at each rising edge of the clock CLK.The cell array is accessed with a one-clock delay, and the read data is taken into the register 28 with a further one-clock delay. This is done every time the rising edge of .

〔Example〕

Registers 32 and 34 take in the outputs of the row decoder 12 and column decoder 14, and can be constructed from a group of flip-flops. The output of the row decoder 12 is only the number of word lines in the memory cell array 10, and the output corresponding to the selected word line is H, the rest are all high, etc. Therefore, the number of Frithop flops in the register 32 is also word line. There are as many lines as there are, and the above H and L of the decoder output are used as the clock CL.
K is taken in and a word driver (not shown) is controlled. Register 34 also follows this. Register 28 is 1
If it is a bit output type, all you need is one flip-flop. If it is a one-word, 8-bit output type, it will consist of eight flip-flops.

In addition to inputting the row address and column address to access the memory cell array at the same time, there are also memories in which the row address and column address are input at a time lag, and these row and column addresses are further divided. There is also memory for sequential input. Column selection can be delayed from row selection, so if a row address is sent first, it is sent to the row decoder 12 via register 22, and the next column address sent is sent to register 22.
The column decode output may be sent to the column decoder 14 via the column decoder 14, and the column decode output may be taken into the register 34 one cycle later than the row decode output into the register 32. In this case, the loading of read data into the register 28 is delayed by one cycle, but since the amount of processing in one cycle is reduced, it is possible to shorten the clock cycle and increase the speed. [Effects of the Invention] As explained above, according to the present invention, a faster synchronous memory can be provided.

Compared to conventional synchronous memory, the synchronous memory of the present invention requires a large number of registers. However, the clock frequency can be increased and the speed is 3a% per clock cycle.
It is possible to shorten the length to a certain extent.

Although it does not shorten the time from when an address is given to when read data is obtained, it can increase the amount of read/write data within a certain period of time, which is advantageous for communication buffers, etc.

[Brief explanation of the drawing]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is an explanatory diagram of write/successive operation, and Fig. 3 is an explanatory diagram of a conventional synchronous memory. In FIG. 1, 10 is a memory cell array, 12 and 14 are address decoders, and 16 are sense amplifiers and write amplifiers.

Claims (1)

[Claims] 1. Address decoder for synchronous semiconductor memory (12, 1
4) and the memory cell array (10).
2, 34), the address decoder decodes the address, and in response to the decoded output, the register selects the word line and bit line of the memory cell array. When the register makes the selection, the address decoder 1. A semiconductor memory device characterized in that an address decoder and a register are operated in parallel so that the address decoder and the register are operated in parallel so that the address decoder and the register start decoding operation.