JPH02235339A - Bipolar transistor - Google Patents

Abstract

PURPOSE:To improve breakdown voltage by arranging an electrode, via an insulating film, on the surfaces of a collector region and a base region for a vertical structure bipolar transistor, and applying an potential equal to the base region to the electrode. CONSTITUTION:In an n-type collector region 3, a p-type emitter region 8 is formed; therein a p-type base region 8 is formed; and further therein an n-type emitter region 9 is formed. The surfaces of these regions are covered with an insulating film 10. On the domain containing the peripheral part of a region 8 being a pn junction surface between both regions of surfaces of the region 3 and the region 8, an electrode 7 is arranged so as to sandwich the film 10. An electric potential nearly equal to that of the region 8 is applied to the electrode 7. By the effect of the caused electrostatic induction via the film 10, by the potential of the electrode 7, the spread of a depletion layer DL in the region 3 is not furthered in the longitudinal direction but furthered in the lateral direction on the surface part. As a result, the depletion layer DL turns to a state shown by figure, and the radius of curvature R of the bottom corner becomes large, so that electric field concentration is relieved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a bipolar transistor suitable for high voltage transistors for integrated circuit devices, etc. It relates to a device comprising a base region made of a conductivity type and an emitter region made of one conductivity type within the base region. [Prior Art] As is well known, bibolar transistors are basic circuit elements widely used in bibolar type and BiMOS type integrated circuit devices, but recently bibolar transistors have been incorporated on the output side of these devices. Increasingly, loads are being driven. Therefore, bipolar transistors are often required to have high withstand voltage and large current performance, and for this reason various improvements have been made in the past. Figures 4 and 5
The figure shows a typical conventional structure. Figure 4 shows an np with a graph-tose structure suitable for high voltage applications.
n transistor is shown incorporated into an integrated circuit device. After pre-diffusing the buried layer 2 in a strong n-type in a predetermined range on the surface of a p-type base Fil for an integrated circuit device, the epitaxial N3 is grown in an n-type, and surrounds a predetermined range from the surface. Separation layer 4 is made of strong p-type base #Fi. The epitaxial layer 3 is junction-separated from the base layer 1 into island-like regions by deep diffusion so as to reach 1, and a bibolar transistor is fabricated using this region as a collector region.

Since the transistor shown in the figure is vertical, in order to lead out the collector terminal C from the buried layer 2, the strong n-type low resistance layer 5 is deeply diffused and connected to the buried layer 2. Next, a p-type graft base region 6 is deeply diffused with a low impurity concentration in an annular pattern surrounding the area where the base mochi 8 is to be formed, and the p-type base region 8 is placed so as to overlap with the inner periphery of the p-type graft base region 6. The emitter region 9 is diffused to a shallower point than that, and a strong n-type emitter region 9 is formed inside it. Collector C. Terminals for base B and emitter E are derived by bringing a metal electrode film, which is omitted from the diagram for simplicity, into conductive contact with the surface of the corresponding area within a window formed in the insulating film 10 such as an oxide film. ．． As is well known, when a high voltage is applied between the collector terminal C and the base terminal B, the electric field tends to concentrate at the bottom peripheral corner of the base nozzle area 8, and the withstand voltage tends to drop. Since the graft TiJ castle 6 with a low impurity concentration is deeply diffused to surround the corner and has a large radius of curvature, electric field concentration is alleviated and the withstand voltage value is improved. In FIG. 4, the flow of electrons e is shown by thin arrows, and the resulting current flows not only at the bottom of the emitter region 9 but also in a fairly concentrated manner at the periphery of the bottom as shown in the figure. In the groove structure of the bibolar transistor shown in FIG. 5, a plurality of inter-emitter regions 9 are formed in the base neck region 8 in order to increase the current contribution of the bottom peripheral portion of the emitter region 8. This structure allows transistors with large current capacity to be built into a small chip area. Of course, by providing the graft region 6 of FIG. 4 around the periphery of the base region 8 of the transistor of FIG. 5, the withstand voltage value can be improved. [Problems to be Solved by the Invention] As mentioned above, the graft base crossroad shown in Fig. 4 is a very effective means for increasing the withstand voltage, but in order to increase the withstand voltage with this means, it is necessary to There is a problem in that the chip area must be increased, and the chip area becomes considerably large, especially when it is desired to increase the withstand voltage value beyond ioov, or to simultaneously achieve high withstand voltage and large current capacity. In other words, the graft region 6 shown in FIG. 4 is not effective unless it is made with a radius of curvature large enough to alleviate electric field concentration.
For this purpose, the depth of diffusion in the longitudinal direction must be made sufficiently large according to the required withstand pressure value, and as a result, the diffusion also spreads in the lateral direction. Furthermore, as can be seen from Fig. 4, the graph} 61 region 6 protrudes downward from the bottom of the base research region 8, and the flow of electrons e from the bottom corner of the emitter region 9 is obstructed by this. Since the current capacity is reduced, it is necessary to sufficiently separate the graft region 6 from the emitter region 9 in the lateral direction, which further increases the chip area. Of course, similar problems arise when increasing the withstand voltage of the bibolar transistor with the large current capacity structure shown in Figure 5. The present invention solves this problem and achieves high voltage resistance. kuni io
The purpose of this invention is to obtain a bipolar transistor having a structure in which the chip area can be reduced compared to the conventional one when increasing the withstand voltage value beyond OV, and at the same time, the current capacity can be increased as much as possible. [! [Means for Solving Problem 1] According to the present invention, this object is achieved by forming a collector region of one conductivity type, an inter-base region formed in the collector region of the other conductivity type, and a base region in the base region. For a bipolar transistor with a vertical structure including an emitter region made of one conductivity type, an electrode is provided facing the collector eMM and the surface of the base region in a range including at least the periphery of the base region with an insulating film interposed therebetween. This is achieved by providing a potential approximately equal to the base nodal range to tFi. Note that it is most preferable that the electrode in the above structure be made of polycrystalline silicon, similar to the gate of a field effect transistor. In principle, this electrode is connected to the same potential as the base M region, but depending on the applied circuit, it may be desirable to connect it to the same potential as the emitter region. An oxide film is suitable for the insulating film under this electrode, and its thickness may be uniform, but it is better to form the part above the collector region thicker than the vicinity of the periphery of the base region to reduce depletion in the collector region. This may be desirable in order to moderate the spread of the layer. Most simply, the present invention is applicable to bibolar transistors in which a single or multiple emitter regions are formed in a single base region, and also to bipolar transistors in which a single emitter region is formed in each of a plurality of base regions. This also applies to a structure in which a stripe-shaped electrode is provided in common to adjacent base regions.In the latter case, an annular electrode can be provided to surround the base region group from the outside. In some cases, it may be advantageous to provide a graft region instead of this annular single pole. Furthermore, in implementing the present invention, as in a field effect transistor, an electrode corresponding to the gate thereof is used as a mask,
It is most advantageous to create the base and emitter regions by so-called self-aligned diffusion using ion implantation. At this time, the electrode is coated with an insulating film not only on at least a portion of the surface including the periphery of the collector region and the base region, but also on a portion of the surface including the periphery of the base and emitter region. It will be set up so that they can face each other through the [Function] As is well known, the breakdown voltage value of a bipolar transistor is usually the maximum voltage that can be applied between the collector nodal region and the base region in the off state, and when this voltage is applied, the pn junction surface of both regions becomes depleted. The depletion layer mainly spreads within the collector battle zone, but if this depletion layer does not spread sufficiently, the electric field will concentrate at the bottom corners of the base region, reducing the withstand voltage value, as described above. The present invention improves the withstand voltage value by promoting the expansion of this depletion layer by using the electrodes having the above-mentioned structure.The effect thereof will be explained with reference to FIG. In FIG. 1(a), as in FIG. 4, a p-type base region 8 is located within an n-type collector region 3. Further, an n-type emitter region 9 is formed in each of them. The surfaces of these subregions are covered with a thin insulating film 10, which is usually an oxide film, and cover an area including the periphery of the base region 8, which is the pn junction between the two heads of the collector region 3 and the surface of the base region 8. , this insulation 11! I! The electric conductor according to the present invention made of polycrystalline silicon or the like is sandwiched between 10 and 10 mm. i7 is provided. Furthermore, in the present invention, a potential approximately equal to that of the base region is applied to this electrode 7. Insulating film 1 due to the potential of this electrode 7
The spread of the depletion layer υL on the surfaces of the collector region 3 and the base region 8 is influenced by electrostatic induction through the base region 8 which is at the same potential as the electrode 7.
Collector MJ, which has the opposite conductivity type, is slightly suppressed on the side.
On the i13 side, it is encouraged. On the other hand, a depletion layer DE. The spread of is, of course, unrelated to the existence of 74 poles. In this way, the spread of the depletion layer DL in the collector region 3 is not promoted in the vertical direction, but is promoted in the lateral direction at the surface, and as a result, the shape of the depletion layer DL is shown with hatching in the figure. As shown in the figure, the radius of curvature R of the bottom corner becomes much larger than the radius of curvature r of the bottom corner of the base nodding region 8, thereby significantly relaxing the electric field concentration.
Note that the spread of the depletion layer DL on the surface of the collector region 3 differs slightly depending on the thickness of the dead-green atO layer, but it can be controlled fairly accurately by adjusting the width of the electrode 7. ．． As can be seen from this, the electrode 7 according to the present invention has a function equivalent to that of the conventional graft base region in terms of alleviating the electric field concentration at the bottom corner of the base region and improving the withstand voltage value.
As can be easily seen from the figure, unlike this, the flow of electrons e from the bottom corner of the emitter region 9 is not obstructed. Therefore, the present invention has the feature that it is more suitable for large currents than the graft-based structure. ．． Therefore, in the present invention, there is no problem in overlapping the electrode 7 with the emitter region 9; rather, by doing so, the base region 8 and the emitter region 9 can be self-aligned by ion implantation using J47 as a mask. It can be built into the collector area 3. This will make production easier, and will also improve collector area 3 and eminter area 9.
This has the advantage of being able to narrow the width of the surface of the base castle 8 between the two. Of course, in this case, the surface of the base region 8 is covered with the electrode 7, but the fact that the electrode 7 suppresses the spread of the depletion layer OL on the surface of the base region 8 works advantageously in this case. In the structure shown in FIG. 1(b) which is applicable to the present invention, a plurality of structures in which emitter regions 9 are built into the base region 8 are provided, and the electrodes 7 are common to the structure in which the electrodes 7 are placed next to each other as shown in the figure. It is set up in By selecting the mutual interval between the two base nodule regions 8 to be sufficiently narrow, the chip area is reduced as much as possible, and the depletion layers DL extending from both base regions 8 into the collector nodule region 3 are fused together as shown in the figure. By making the radius of curvature R larger than that shown in FIG. 1(a), the withstand pressure value can be further improved. Of course, even in this structure, the above-mentioned advantages can be utilized by forming the base head region 8 and emitter head region 9 in a self-aligning manner using the electrode 7 as a mask. [Example] Hereinafter, an example of the present invention will be specifically described with reference to FIGS. 2 and 3. Parts corresponding to the previous figures 4 and 5 in these figures are given the same reference numerals.
Fig. 2 shows an embodiment corresponding to the previous Fig. 1 (a), and the same figure (al shows the cross section, and Fig. 2 (b) shows the top surface. Fig. 2 (a) In this example, the integrated circuit device substrate 1 is p-type and has an impurity concentration of about IQI! atoms/C, and the n-type buried layer 2 on its surface has a high impurity concentration of 1O'' atoms/cj or more. A high-resistance epitaxial layer 3, which will become the n-type collector region, is formed on top of the pre-diffused n-type collector region with an impurity concentration of about 1QI4 atoms/C, for example, and a thickness of about 20 μm or more for high breakdown voltage applications. As usual, the P-type division layer 4 is grown from the surface of the epitaxial layer 4 to surround the area where the bipolar transistor is to be fabricated, as shown in FIG. The bipolar transistor is fabricated using the epitaxial layer 3 surrounded by the isolation layer 4 as a collector castle, and for this purpose, an n-type low The resistance layer 5 has a high impurity concentration of 101 atoms/C1 or more and is diffused in a striped pattern in this example as shown in FIG. A silicon oxide film is usually used for the insulating wA11 on the underside of the electrode 7, and a desired breakdown voltage value is formed on the surface of the central part of the collector region 3 by dry oxidation, for example. However, in this example, prior to this, so-called LOGOSI is applied so as to continuously cover the peripheral edge of the collector region 3 and the surface of the separation layer 4.
I! A thick insulating film 12 having a thickness of, for example, about 1 pm is formed by a steam oxidation method or the like. The electrode 7 according to the present invention is preferably made of polycrystalline silicon, similar to the gate of a field effect transistor, and is grown by the usual CVD method to a thickness of, for example, about 0.5 nm, and then photo-etched. In this example, it is formed into an annular shape, as shown by the hatched sag in the same figure.
Note that the electrode 7 in this example is formed on a thin insulating II 5111 and a thick insulating film 12, as can be seen from FIG. This thin insulation Hall has a high effect of expanding the depletion layer DL along the surface of the collector region 5 below the electrode 7, and is a thick insulation! At I12, this effect becomes slightly smaller.
In this embodiment, the impurities for the base region 8 and the emitter region 9 are both diffused by ion implantation using the electrode 7 as a mask, and the diffusion pattern is such that the base region 8 is rectangular and the emitter region is rectangular as shown in the figure. Region 9 is a rectangle with a window in the center.

The p-type base region 8 is 10 1? For example, at a depth of 3μ with an impurity concentration of about atoms/cd, the Ω-shaped emitter nodule region 9 is lO! Each layer is formed at a depth of, for example, 2 μm with an impurity concentration of about 6 atoms/cd. At this time, when boron is used as a p-type impurity and phosphorus is used as a 50-type impurity as usual, each impurity is individually thermally diffused each time ion implantation is performed, and instead of phosphorus, arsenic, etc., which has a slow diffusion rate, is used. When impurities are used, simultaneous thermal diffusion is performed after ion implantation of both impurities.

As a result, the entire periphery of the base region 8 and a part of the outer periphery of the emitter nodding region 9 are diffused so as to go under the thin insulating film 11 as shown in the figure, and therefore the outer periphery of the emitter region 9 is then diffused into the collector. It is placed under the thin insulation W111 so that the depletion layer DL can easily spread toward the region 3. After diffusion of base region 8 and emitter 9K region 9,
An upper insulating film l3, which is usually an oxide film, is deposited on the entire surface,
Electrodes WA2l-23 are provided in the windows opened at key points as shown in the figure. The electrode ll21 for the collector terminal C is in conductive contact with the low resistance layer 5, the electrode @22 for the emitter terminal E is in conductive contact with the emitter region 9, and the t for the base terminal B is in conductive contact with the low resistance layer 5.
The illI 23 is in conductive contact with the central part of the base nodule 8, which in this example corresponds to the window of the emitter nodule 9, and the electrode 7, so that the electrode 7 is placed at the same potential as the base region 8. In FIG. 2 (al), the spread of the depletion layer DL in the off state of the bipolar transistor in this embodiment is shown with hatching. Since it is suppressed by the electrode 7 on the lower side of the insulation Ll! 11, there is very little overall, but from the outer peripheral edge of the emitter head wall 8 toward the collector region 3, it is promoted laterally by the electrode 7, and the thin insulation film 11
It extends beyond the thick insulating film l2 to the underside of the thick insulating film l2, and plays the role of alleviating local electric field concentration as described above. 2. The surface potential of the collector robust region 3 increases as it goes from the periphery of the base so-called region 8 to the tip of the depletion layer OL, but since the tip of the depletion layer OL sinks under the thick insulation 11l12, the breakdown voltage of the electrode 7 is Guaranteed by this thick 1812. Further, the spread of the depletion layer DL is not promoted much under the thick insulation Pa12, and the tip thereof is, for example, the low resistance layer 5.
This prevents so-called bunch-through from occurring. Further, in this embodiment, a single emitter region 9 is formed in the base area 8, but by forming a plurality of emitter regions concentrically to increase the total peripheral length, it is possible to It is possible to increase the current capacity without reducing the withstand voltage value of the Bora transistor.

Fig. 3 shows an embodiment corresponding to the previous Fig. 1 (Fig. In order to avoid unnecessary complication, the upper insulating films 13 and 1 in FIG.
Please note that the t-pole membrane is omitted in this Figure 3. In this embodiment, the base region 8 and emitter region 9 of the striped pattern are paired and the collector region 3
A plurality of striped patterned electrodes 7 are provided in common for adjacent pairs of base regions 8 and emitter regions 9. In addition, graft territory 6 is provided for the pair at both ends. In FIG. 3(a), the process is the same as the previous embodiment until the low resistance layer 5 is expanded in the collector region 3, and then the P
A graph of the shape} 61 area 6 surrounds the range to be diffused by a plurality of base areas 8 and emitter areas 9 in a ring shape as shown in the figure, for example, IQIS, 101! It is diffused to a depth of 4 to 6 nm depending on the required breakdown voltage value at an impurity concentration of atoms/d. Next, as in the previous example, thin insulation 1! Ill and thick insulation lI
After covering the surface with IH 11, a plurality of electrodes 7 are provided in a striped pattern mainly on the thin IH 11. On this occasion,
As can be seen from Figure 1), each electrode 7 is patterned so that the upper and lower ends of the figure are above area 6 of the graph, or so as to protrude slightly from it. In this example as well, the p-type impurity for the base nozzle region 8 and the n-type impurity for the emitter region 9 are introduced by the ion implantation method using the electric scraper 7 as part of the mask, and each time they are individually thermally diffused. At this time, the base region 8 is formed under the electrode 7, and is formed so as to overlap the graft region 6 in other portions. The emitter region 9 is formed in each base region 8, and as can be seen from the same figure, a part or most of its periphery is formed under the electrode 7. As shown in FIG. 3(G), the collector terminal C is connected to the collector region 3 through the buried layer 2, and the emitter terminal E is connected to the plurality of emitter regions 9 and From the plurality of electrodes 7, the base terminals B are taken from the plurality of base regions 8, respectively. Therefore, in this embodiment the electrode 7 has an emitter region 9 at approximately the same potential as the base region.
is placed at the same potential as This is advantageous in constantly stabilizing the potential of the electrode 7 when the base terminal B can be at a floating potential during operation of the transistor. Figure (a) shows the depletion layer L during off-operation of the transistor with hatching. In this embodiment, the depletion layers OL fuse together between the base regions 8 as shown in the figure.
Since the depletion layer DL spreads into the graft region 6 from the base region 8 at the end, a high breakdown voltage can be obtained.

Furthermore, since the total peripheral length 1 of the emitter region 9, and therefore the total length of its bottom corner, is larger than in the previous example, a large current capacity can be obtained. In the hyperpolar transistor according to this embodiment configured as described above, by creating several pairs of space regions 8 and emitter regions 9 within a chip area of, for example, 100 x 300 μm, It can have a high withstand voltage value of about 200 µA and a large current capacity of about 100 µA, and a current amplification factor of 100 to 150 can be obtained. Note that the graph of this example} 8M region 6 can be replaced with electrode 7. In this case, the electrode 7 is a single electrode in the form of a plurality of striped electrodes suspended between opposite sides of a frame-shaped electrode, and a base region 8 and an emitter region 9 are formed from each window. As can be seen from this, the present invention is not limited to the embodiments described above, and can be implemented in various ways. For example, since it is sufficient to apply approximately the same potential to the electrode as the base region, there is practically no difference whether the electrode is connected to the base region or the emitter region. Although it is advantageous to form the electrodes with polycrystalline silicon as in the embodiments when building the bibolar transistor according to the present invention into a BiMOS circuit, etc., it is advantageous to form the electrodes with polycrystalline silicon as in the embodiment. There is no problem even if it is composed of The electrode pattern, the type and thickness of the insulating film, the conductivity type of each region, the pattern of the base region and emitter head region, the impurity concentration, the diffusion depth, etc. in the examples are just examples, and in reality, high-bore It should be selected appropriately in accordance with the ratings and characteristics required of the transistor. Furthermore, as described in part in the examples, it is possible to appropriately combine the structure based on the present invention with a structure based on the prior art such as a graft region, and effectively utilize part or all of the effects within the gist of the present invention. can. [Effects of the Invention] As is clear from the above description, in the present invention, a collector region of one conductivity type, a base region of the other conductivity type built into the collector region, and one IT For a bipolar transistor having a shaped emitter region, a t-pole facing each other via an insulating film is provided in a range including at least the periphery of the base region on the surface of the collector M region and the base region. Since a potential approximately equal to that of the base region is applied, the potential applied to this electrode causes the depletion layer to spread laterally from the periphery of the emitter region under the insulating film toward the collector region. This effectively alleviates the electric field concentration that occurs in In addition, the expansion of the depletion layer does not impede the emitter current path, making it possible to improve current capacity compared to conventional methods. Furthermore, since the spread of the depletion layer can be accurately controlled by the pattern provided to the electrode, there is no need to take a margin in the pattern dimension, and the chip area can be reduced compared to the conventional method. For example, even in the simplest example with a single base region and emitter region shown in Figure 2, a high withstand voltage value of 180μ can be obtained, and the t flow capacity is improved by more than 20% compared to the conventional one with the same chip area. can.

In addition, a plurality of pairs of base regions and emitter regions are provided,
According to the aspect in which electrodes are provided in common in adjacent pairs, the length of the peripheral edge of the emitter region can be increased to increase the current capacity, and the withstand voltage value can also be further improved. For example, even when several pairs of base regions and emitter regions are provided as shown in Fig. 3, it is easy to obtain a high withstand voltage value of about 200μ, and at the same time, the current capacity can be reduced by about 50% compared to conventional methods with the same chip area. It can be improved. The present invention is applicable not only to bibolar transistors in general, but is particularly advantageous when incorporated into BiMOS integrated circuit devices, and can be applied to the above-mentioned high breakdown voltage. By increasing the current and reducing the size, it is possible to directly drive human loads,
We can contribute to its further development and spread.

[Brief explanation of drawings]

1 to 3 relate to the present invention, and FIGS. 1(a) and (bl) are cross-sectional views showing essential parts of the basic structure of the bibolar transistor according to the present invention, and FIGS. 2(a) and (bl).
FIGS. 3(a) and 3(b) are a sectional view and a top view showing different embodiments of the present invention, respectively. FIG. 4 and subsequent figures relate to the prior art. FIG. 4 is a cross-sectional view of a conventional high-voltage bipolar transistor, and FIG. 5 is a cross-sectional view of a conventional high-current bipolar transistor. In the figure, ■ = semiconductor substrate for integrated circuit device, 2: buried layer, 3: collector region or epitaxial layer, 4: separation layer, 5: low resistance layer for collector terminal, 6: graft region, 7: M1 pole , 8: base region, 9: emitter region, lO: insulating film,
l1: Thin insulating film, l2: Thick insulating film, 13: Upper insulating film, 2l: Electrode film for collector terminal, 22: Electrode film for emitter terminal, 23: Electrode 8i film for base terminal, B: Base terminal, C: Collector terminal, OL double depletion layer, E: emitter terminal, e: electron, R: radius of curvature of the depletion layer, r: radius of curvature of the bottom corner of the base region. Collector Territory Flexta Ode No. 2B! a Figure 1 Figure 4

Claims (1)

[Claims] It includes a collector region of one conductivity type, a base region formed into the collector region from the surface of the other conductivity type, and an emitter region formed from the surface of the one conductivity type into the base region. The invention is characterized in that electrodes are provided on the surfaces of the collector region and the base region in a range including at least the periphery of the base region, facing each other with an insulating film interposed therebetween, and a potential approximately equal to that of the base region is applied to the electrodes. bipolar transistor.