JPH0223629A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0223629A
JPH0223629A JP17472988A JP17472988A JPH0223629A JP H0223629 A JPH0223629 A JP H0223629A JP 17472988 A JP17472988 A JP 17472988A JP 17472988 A JP17472988 A JP 17472988A JP H0223629 A JPH0223629 A JP H0223629A
Authority
JP
Japan
Prior art keywords
substrate
layer
insulating film
silicon
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17472988A
Other languages
Japanese (ja)
Inventor
Tsuneo Hamaguchi
恒夫 濱口
Toshihide Kuriyama
敏秀 栗山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17472988A priority Critical patent/JPH0223629A/en
Publication of JPH0223629A publication Critical patent/JPH0223629A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To shorten the production time, and to polish a semiconductor substrate in uniform thickness by laminating an silicon substrate and a support substrate isolated by a dielectric. CONSTITUTION:An silicon dioxide film region 2 as an annular field insulating film is formed under the surface of an n-type silicon sub strate 1. An silicon dioxide laminated film 3 is shaped onto the surface of the n-type silicon substrate 1, and the surface is flatten ed through polishing. An silicon support substrate 4, to the surface of which hydrophilic treatment is executed and the type of an impurity of which is not specified, is prepared, fast stuck to the n-type silicon substrate 1, and silanol-joined. The rear of the n-type silicon substrate 1 is polished, the silicon dioxide film region 2 is exposed, and an element forming region 1a surrounded by the silicon dioxide film region 2 is shaped. An impurity is introduced to the ground surface of the n-type silicon substrate 1 and p layers 5, 5 in desired depth are formed, and an n<+> layer 7 is shaped to the p layer 6. A gate electrode G is formed onto the p layer 6, all anode electrode A to the p layer 5 and a cathode electrode C onto the n<+> layer 7 respectively.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に、誘電体分
離構造を用いる半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device using a dielectric isolation structure.

〔従来の技術〕[Conventional technology]

従来、誘電体分離法を用いる半導体装置の半導体装置の
製造方法としては、多結晶シリコン層を支持基板とした
ものが知られており、その技術は例えばエヌイーシー・
リサーチアンドデベロプメント(NECRe5erch
 &  Deve!opment)第57巻、1980
年、第39頁に発表されている。
Conventionally, as a method for manufacturing a semiconductor device using a dielectric separation method, a method using a polycrystalline silicon layer as a support substrate has been known, and this technology is, for example, developed by N.C.
Research and Development (NECRe5erch)
& Deve! opment) Volume 57, 1980
Published in 2013, page 39.

第3図(a)〜(d)は従来の半導体装置の製遣方法の
一例を説明するための工程順に示した半導体チップの断
面図である。
FIGS. 3(a) to 3(d) are cross-sectional views of a semiconductor chip shown in order of steps to explain an example of a conventional method for manufacturing a semiconductor device.

まず、第3図(a)に示すように、n型シリコン基板1
1に選択エツチングを行なって、素子分離用の講10を
形成した後、表面を熱酸化することにより、酸化膜12
aを形成する。
First, as shown in FIG. 3(a), an n-type silicon substrate 1
After selectively etching 1 to form a layer 10 for element isolation, the surface is thermally oxidized to form an oxide film 12.
form a.

次に、第3図(b)に示すように、溝10aが形成され
た二酸化シリコン膜12aの表面に多結晶シリコン層1
3を数百μmの厚さに堆積して渭10aを埋める。
Next, as shown in FIG. 3(b), a polycrystalline silicon layer 1 is formed on the surface of the silicon dioxide film 12a in which the groove 10a is formed.
3 is deposited to a thickness of several hundred μm to fill the armature 10a.

次に、第3図(C)に示すように、その多結晶シリコン
層13を支持基板として、半導体基板11の裏面を研摩
除去して、単結晶のシリコンアイランドの素子形成領域
11aを形成する。
Next, as shown in FIG. 3C, using the polycrystalline silicon layer 13 as a support substrate, the back surface of the semiconductor substrate 11 is polished away to form a single-crystal silicon island element formation region 11a.

次に、第3図(d)に示すように、素子形成領域11a
にアノードA、ゲートG及びカソードCを有するサイリ
スタ8aを形成することにより、半導体装置が完成する
Next, as shown in FIG. 3(d), the element formation region 11a
By forming a thyristor 8a having an anode A, a gate G, and a cathode C, a semiconductor device is completed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置の製造方法では、支持基板と
して用いる多結晶シリコン層を数百μm堆積するのに多
くの時間と費用がかかること、また多結晶シリコン層が
均一に厚さになっていないこと、更に、多結晶シリコン
層の成長の工程で成長面の反対面にも多結晶シリコン層
が成長する等の理由で、単結晶シリコンからなる半導体
基板を均一の厚さに研摩することができないこと等多く
の問題があった。
In the conventional semiconductor device manufacturing method described above, it takes a lot of time and money to deposit several hundred micrometers of polycrystalline silicon layer used as a supporting substrate, and the polycrystalline silicon layer does not have a uniform thickness. Furthermore, it is not possible to polish a semiconductor substrate made of single crystal silicon to a uniform thickness because the polycrystalline silicon layer grows on the opposite side of the growth surface during the process of growing the polycrystalline silicon layer. There were many problems.

本発明の目的は、製造時間が短縮されかつ半導体基板が
均一の厚さに研摩できる半導体装置の製造方法を提供す
ることにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that reduces manufacturing time and allows a semiconductor substrate to be polished to a uniform thickness.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の第1の半導体装置の製造方法は、(A)  半
導体基板の一主面に素子形成領域を囲んで表面からフィ
ールド絶縁膜領域を形成する工程、 (B)  前記半導体基板の表面及び前記フィールド絶
縁膜領域の表面に絶縁膜を形成する工程、 (C)  前記絶縁膜の表面に半導体支持基板を密着し
、熱処理して張合せ基板を形成する工程、 (D)  前記半導体基板の他の主面を研摩して前記フ
ィールド絶縁膜領域を露出し島状の素子形成領域を形成
する工程、 を含んで構成されている。
A first method for manufacturing a semiconductor device of the present invention includes: (A) forming a field insulating film region from the surface surrounding an element formation region on one principal surface of the semiconductor substrate; (B) forming a field insulating film region from the surface of the semiconductor substrate and the a step of forming an insulating film on the surface of the field insulating film region; (C) a step of closely adhering a semiconductor support substrate to the surface of the insulating film and performing heat treatment to form a laminated substrate; (D) a step of forming a bonded substrate on the surface of the semiconductor substrate; The method includes the step of polishing the main surface to expose the field insulating film region and forming an island-shaped element formation region.

本発明の第2の半導体装置の製造方法は、前記(B)項
に代えて、前記半導体基板の表面及び前記フィールド絶
縁膜領域の表面に絶縁膜と多結晶シリコン層の積層を形
成する工程を含んで構成されている。
A second method for manufacturing a semiconductor device of the present invention includes a step of forming a stack of an insulating film and a polycrystalline silicon layer on the surface of the semiconductor substrate and the surface of the field insulating film region, in place of the above item (B). It is composed of:

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(e)は本発明の第1の実施例を説明す
るための工程順に示した半導体チップの断面図である。
FIGS. 1(a) to 1(e) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.

まず、第1図(a)に示すように、n型シリコン基板1
の表面下に素子形成領域を囲む局所的な熱酸化法、また
はシリコン基板を局所的にエツチングした後CVD法に
よって環状のフィールド絶縁膜となる二酸化シリコン膜
領域2を形成する。
First, as shown in FIG. 1(a), an n-type silicon substrate 1
A silicon dioxide film region 2, which will become an annular field insulating film, is formed below the surface of the silicon substrate by a local thermal oxidation method surrounding the element formation region, or by a CVD method after locally etching the silicon substrate.

次に、第1図(b)に示すように窒化シリコン二酸化シ
リコン積層膜3をn型シリコン基板1の表面に形成し、
表面を研摩により平坦にする。
Next, as shown in FIG. 1(b), a silicon nitride silicon dioxide laminated film 3 is formed on the surface of the n-type silicon substrate 1,
The surface is made flat by polishing.

次に、表面を親水性処理を施した不純物の型を特定しな
いシリコン支持基板4を用意し、n型シリコン基板1に
密着させ、シラノール接合を行なう。
Next, a silicon support substrate 4 whose surface has been subjected to hydrophilic treatment and whose impurity type is not specified is prepared, and brought into close contact with the n-type silicon substrate 1 to perform silanol bonding.

親水性化処理は、ウェーハ表面に酸化膜を設ける処理で
あり、方法としてはシリコン基板4の表面を熱酸化する
とか、過酸化水中に浸すことによってなされる。
The hydrophilic treatment is a treatment for forming an oxide film on the wafer surface, and is performed by thermally oxidizing the surface of the silicon substrate 4 or immersing it in peroxide water.

シラノール接合は、ウェーハ面同志を密着させ、例えば
1000°C熱処理を行なうことにより、ウェーハ表面
の水酸基同志が熱処理によってH2Oとなり、脱水縮合
を起す結果、ウェーハの接合が行なわれるということを
いう。
Silanol bonding is a process in which the wafer surfaces are brought into close contact with each other and heat treated at 1000°C, for example, so that the hydroxyl groups on the wafer surface become H2O through the heat treatment, causing dehydration and condensation, resulting in the bonding of the wafers.

この方法は、例えばアイ・イー・イー・イー。This method is, for example, I.E.I.E.

インターナショナル、エレクトロン、デバイスミ−テン
グ(IEEE、Internasional Elec
tron DeviceMeeting)のテクニカル
ダイジェスト(TechnicalDigest) 、
1985年、第684〜687頁に報告されている。
International, Electron, Device Meeting (IEEE, International Elec)
tron DeviceMeeting) Technical Digest,
1985, pp. 684-687.

次に、第1図(d)に示すように、n型シリコン基板1
の裏面を研摩し二酸化シリコン膜領域2を露出させ二酸
化シリコン膜領域2に囲まれた素子形成領域1aを形成
する。
Next, as shown in FIG. 1(d), an n-type silicon substrate 1
The back surface of the silicon dioxide film region 2 is polished to expose the silicon dioxide film region 2, thereby forming an element formation region 1a surrounded by the silicon dioxide film region 2.

この研摩法は化学液にアミン水溶液を用いることにより
二酸化シリコン膜領域2をまったく加工しないため、二
酸化シリコン膜領域2の表面で容易に研摩加工を止める
ことができる。
Since this polishing method uses an amine aqueous solution as the chemical solution and does not process the silicon dioxide film region 2 at all, the polishing process can be easily stopped at the surface of the silicon dioxide film region 2.

次に、第1図(e)に示すように、n型シリコン基板1
の研摩面に不純物を導入して所望の深さの2層5,6を
形成し、さらに2層6にN+層7を形成する。
Next, as shown in FIG. 1(e), an n-type silicon substrate 1
Impurities are introduced into the polished surface to form two layers 5 and 6 of a desired depth, and an N+ layer 7 is further formed on the second layer 6.

次いで、2層6上にゲート電極G、P層5にアノード電
極Aを、さらにN+層層上上カソード電極Cをそれぞれ
形成することにより、誘電体分離の半導体装置を完成さ
せる。
Next, a gate electrode G is formed on the second layer 6, an anode electrode A is formed on the P layer 5, and an upper cathode electrode C is formed on the N+ layer, thereby completing a dielectrically isolated semiconductor device.

第2図(a)〜(e)は本発明の第2の実施例を説明す
るための工程順に示した半導体チップの断面図である。
FIGS. 2(a) to 2(e) are cross-sectional views of a semiconductor chip shown in order of steps for explaining a second embodiment of the present invention.

まず、第2図(a)に示すように、第1の実施例と同一
の工程で、n型シリコン基板1の表面下に局部的に二酸
化シリコン膜領域2を形成する。
First, as shown in FIG. 2(a), a silicon dioxide film region 2 is formed locally under the surface of an n-type silicon substrate 1 in the same process as in the first embodiment.

次に、第2図(b)に示すようにn型シリコン基板1の
表面に二酸化シリコン膜3aを形成し、さらにその表面
にCVD法により多結晶シリコン層9を形成する。
Next, as shown in FIG. 2(b), a silicon dioxide film 3a is formed on the surface of the n-type silicon substrate 1, and a polycrystalline silicon layer 9 is further formed on the surface by the CVD method.

次に、第2図(c)に示すように、表面が親水性なシリ
コン支持基板4を多結晶シリコン層5と密着させ、シラ
ノール接合を行なう。
Next, as shown in FIG. 2(c), a silicon support substrate 4 having a hydrophilic surface is brought into close contact with the polycrystalline silicon layer 5, and silanol bonding is performed.

以下、第2図(d)及び(e)示すように、前述の第1
の実施例の(d)及び(e)と同一工程で素子形成領域
1aにサイリスタ8を形成する。
Hereinafter, as shown in FIGS. 2(d) and (e), the above-mentioned first
The thyristor 8 is formed in the element formation region 1a in the same process as in the embodiments (d) and (e).

本実施例では多結晶シリコン層5は研摩により高平坦面
が得られ易く、支持基板4との接合を容易にできる効果
がある。
In this embodiment, the polycrystalline silicon layer 5 can easily be polished to a highly flat surface, which has the effect of facilitating bonding to the support substrate 4.

このように、第1及び第2の実施例においてはシリコン
支持基板4を用いることにより、従来のように多結晶シ
リコン層を堆積する必要はなくなると共に、n型シリコ
ン基板1の裏面をより均一に研摩することが可能となる
As described above, by using the silicon supporting substrate 4 in the first and second embodiments, it is not necessary to deposit a polycrystalline silicon layer as in the conventional method, and the back surface of the n-type silicon substrate 1 can be made more uniform. It becomes possible to polish.

なお、上述の第1及び第2の実施例においては、素子形
成領域1aにサイタリスタを製造する場合について述べ
たが、形成半導体素子はそれまでにとどまらず、本発明
はLOCO8分離を施したMOSFETあるいはバイポ
ーラトランジスタの集積回路の製造にも同様に適用する
ことができる。
In the first and second embodiments described above, a case was described in which a citristor was manufactured in the element formation region 1a, but the semiconductor element to be formed is not limited to that. It can be similarly applied to the manufacture of bipolar transistor integrated circuits.

〔発明の効果〕 以上説明したように、本発明は誘電体で分離されたシリ
コン基板と支持基板とを張合わせることにより容易に形
成することができ、従来のように多結晶シリコン層を堆
積する必要がなくなるため、製造時間が短縮されると共
に、誘電体分離されたシリコン領域の厚さを均一に形成
でき、かつ、その厚さもフィールド絶縁膜領域の二酸化
シリコン膜領域の厚さにより、容易にコントロールでき
るという効果がある。
[Effects of the Invention] As explained above, the present invention can be easily formed by laminating a silicon substrate and a support substrate separated by a dielectric material, and can be easily formed by depositing a polycrystalline silicon layer as in the conventional method. Since this is no longer necessary, manufacturing time is shortened, and the thickness of the dielectrically isolated silicon region can be formed uniformly. It has the effect of being controllable.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(e)は本発明の第1の実施例を説明す
るための工程順に示した半導体チップの断面図、第2図
(a)〜(e)は本発明の第2のの実施例を説明するた
めの工程順、に示した半導体チップの断面図、第3図(
a)〜(d)は従来の半導体装置の製造方法の一例を説
明するための工程順に示した半導体チップの断面図であ
る。 1・・・n型シリコン奉板、1a・・・素子形成領域、
2・・・二酸化シリコン膜領域、3・・・窒化シリコン
膜と二酸化シリコン膜の積層、4・・・シリコン支持基
板、5・・・P層、7・・・n+層、8・・・サイリス
タ、9・・・多結晶シリコン層。
FIGS. 1(a) to (e) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, and FIGS. A cross-sectional view of the semiconductor chip shown in FIG.
1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an example of a conventional method for manufacturing a semiconductor device. 1... N-type silicon plate, 1a... Element formation area,
2... Silicon dioxide film region, 3... Lamination of silicon nitride film and silicon dioxide film, 4... Silicon support substrate, 5... P layer, 7... N+ layer, 8... Thyristor , 9... polycrystalline silicon layer.

Claims (1)

【特許請求の範囲】 1、 (A)半導体基板の一主面に素子形成領域を囲んで表面
からフィールド絶縁膜領域を 形成する工程、 (B)前記半導体基板の表面及び前記フィールド絶縁膜
領域の表面に絶縁膜を形成す る工程、 (C)前記絶縁膜の表面に半導体支持基板を密着し、熱
処理して張合せ基板を形成す る工程、 (D)前記半導体基板の他の主面を研摩して前記フィー
ルド絶縁膜領域を露出し島状 の素子形成領域を形成する工程、 を含むことを特徴とする半導体装置の製造方法。 2、請求項1記載の(B)項に代えて前記半導体基板の
表面及び前記フィールド絶縁膜領域の表面に絶縁膜と多
結晶シリコン層の積層を形成する工程を含むことを特徴
とする半導体装置の製造方法。
[Claims] 1. (A) forming a field insulating film region from the surface surrounding an element formation region on one main surface of the semiconductor substrate; (B) forming a field insulating film region on the surface of the semiconductor substrate and the field insulating film region; a step of forming an insulating film on the surface; (C) a step of closely adhering a semiconductor support substrate to the surface of the insulating film and heat-treating it to form a laminated substrate; (D) polishing the other main surface of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: exposing the field insulating film region to form an island-shaped element formation region. 2. A semiconductor device characterized by including a step of forming a laminated layer of an insulating film and a polycrystalline silicon layer on the surface of the semiconductor substrate and the surface of the field insulating film region in place of item (B) of claim 1. manufacturing method.
JP17472988A 1988-07-12 1988-07-12 Manufacture of semiconductor device Pending JPH0223629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17472988A JPH0223629A (en) 1988-07-12 1988-07-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17472988A JPH0223629A (en) 1988-07-12 1988-07-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0223629A true JPH0223629A (en) 1990-01-25

Family

ID=15983635

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17472988A Pending JPH0223629A (en) 1988-07-12 1988-07-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0223629A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5333590A (en) * 1976-09-10 1978-03-29 Hitachi Ltd Production of substrate for semiconductor integrated circuit
JPS6159853A (en) * 1984-08-31 1986-03-27 Toshiba Corp Structure of silicon crystalline body
JPH01226166A (en) * 1988-03-07 1989-09-08 Seiko Epson Corp Method for manufacturing semiconductor device substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5333590A (en) * 1976-09-10 1978-03-29 Hitachi Ltd Production of substrate for semiconductor integrated circuit
JPS6159853A (en) * 1984-08-31 1986-03-27 Toshiba Corp Structure of silicon crystalline body
JPH01226166A (en) * 1988-03-07 1989-09-08 Seiko Epson Corp Method for manufacturing semiconductor device substrate

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