JPH0223630A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming element isolation.

[Conventional technology 1] In order to miniaturize conventional CMOS type semiconductor devices and improve their reliability, a so-called well isolation method, as shown in Figure 4, has been studied, in which deep trenches are formed on the surface of a semiconductor substrate and filled with an insulator. There is. At this time, element isolation is of course necessary, and techniques for forming two different isolations on the same substrate are also being considered. Examples of these technologies include, for example, Japanese Patent Application Laid-open No. 5
955055 and JP-A-60-25247 are being studied.

[Problem to be solved by the invention] However, among the above-mentioned conventional techniques, Japanese Patent Laid-Open No. 59-550
55 is one of the most common methods, but because the device isolation and well isolation caps are LOGO8, it has the drawback that miniaturization between wells and between elements can only be achieved halfway. are doing. For this reason, although there are not many quality problems, practical application has been delayed.

Furthermore, among the conventional techniques mentioned above, Japanese Patent Application Laid-Open No. 6025247
Since both element isolation and well isolation are groove-drilled type, it is possible to achieve miniaturization between wells and between elements, but if the precision of patterning alignment is not 0, It has drawbacks such as slits and disconnection of the wiring material. For this reason, although it has submicron separation ability, it involves quality problems and is therefore impossible to put into practical use.

The present invention solves the above-mentioned problems, and its purpose is to provide a technology that realizes miniaturization of two different separations on the same substrate without creating a slit-like difference. It's about doing.

[Means for Solving the Problems] The method for manufacturing a semiconductor device of the present invention includes: (1) A semiconductor having a deep groove and a shallow dip on a semiconductor substrate, and having two types of element isolation formed by filling the two grooves. The method for manufacturing the device is characterized by comprising the steps of: a) forming a deep groove, filling more than half of the deep groove, and then forming a shallow immersion; and b) burying the remaining groove part of the deep groove and the shallow immersion part at the same time. shall be.

[Function] When filling deep grooves with etchback, etc., it is difficult to fill them in one step, so the grooves are filled in by performing edgeback in two steps. This second etch-back is also used in the shallow filling process, making it possible to create a CM with almost no difference in dimension conversion.
Two O3 element isolations can be formed.

〔Example〕

Hereinafter, the present invention will be described in detail based on examples.

FIG. 1 is a sectional view of the main parts of the first embodiment of the present invention, in which 1 is a semiconductor substrate, 2 is a silicon oxide film, 3 is polycrystalline silicon, 4 is a photoresist, and 5 is CVD silicon. oxide film, 6 is an N- impurity layer, 7 is a P- impurity layer, 8 is an N+ impurity layer, 9 is a P9 impurity layer, 10 is a first wiring,
11 is a second wiring.

FIG. 2 is a process sectional view of the main part of the first embodiment of the present invention. Here, the steps necessary for forming element isolation will be explained. Therefore, in order to realize a MOS LSI, for example, it is necessary to add the following necessary steps.

First, as shown in FIG. 2(a), a deep groove of, for example, 4 μm is formed in, for example, a silicon substrate (1) by RIE using a photoresist (4) as a mask.

In addition to photoresist, an oxide film may be used as a mask for etching the silicon substrate.

Next, as shown in FIG. 2(b), 2000 CVD silicon oxide films (5) are formed on the surface of the silicon substrate on which the deep grooves have been formed by vapor layer deposition (hereinafter referred to as CVD), and then CVD silicon oxide film (5) is formed by CVD. Polycrystalline silicon (
3) Form 7,000 people.

Next, as shown in FIG. 2C, the polycrystalline silicon is etched back to a depth of about 7,000 mm on the surface of the silicon substrate by, for example, plasma etching, and the silicon oxide film is etched back using, for example, a hydrofluoric acid aqueous solution. Expose the substrate surface by wet etching.

Next, as shown in FIG. 2(d), a silicon substrate (1
), a shallow dip of, for example, 0.8 μm is formed by RIE using the photoresist (4) as a mask.

Of course, an oxide film may be used in addition to the photoresist as a mask for etching the silicon substrate, and the oxide film in this step can also be used before etching the CVD oxide film, so the etching process described above can be used after that. The substrate surface of the silicon oxide film may be exposed by wet etching using, for example, a hydrofluoric acid aqueous solution.

Next, as shown in FIG. 2(e), CVD is applied to the surface of the silicon substrate where the grooves and shallow dips left above the deep grooves are formed.
Form 10,000 oxide films (5).

Next, as shown in FIG. 2(f), the CVD oxide film is etched back to the surface of the silicon substrate by, for example, plasma etching, leaving the CVD oxide film in the trenches and shallow trenches left above the deep trenches.

In the manner described above, two element isolations, deep trench and shallow trench, were formed. Further, in this example, the introduction of impurities necessary for forming the well is performed after forming the deep trench and before the second edge back. In addition, after this, MO5LSI
If a gate oxide film is to be formed, the steps after forming the gate oxide film are continued.

FIG. 3 is a process sectional view of the main part of a second embodiment of the present invention.

After forming as shown in FIG. 2(d), as shown in FIG. 3(a), a silicon oxide film (2 ) is formed by thermal oxidation, 1000 CVD nitride films (12) are formed, and then 4000 polycrystalline silicon (3) are formed on the substrate surface by CVD.

Next, as shown in FIG. 3(b), a thermoplastic resin (1
3) Form.

Next, as shown in Fig. 3(C), the thermoplastic resin is etched back, leaving only the lower part of the step, and using the remaining resin as a mask, polycrystalline silicon is etched into the groove by plasma etching, for example. Leave only for.

Next, as shown in FIG. 3(d), the polycrystalline silicon remaining only in the groove is thermally oxidized in a wet atmosphere at 1000°C to turn it into a thermal oxide film, and the CVD nitride film exposed on the surface is removed. Remove.

In the manner described above, two element isolations, a deep trench and a shallow trench, were formed. Further, in this example, the introduction of impurities necessary for forming the well is performed after forming the deep trench and before forming the CVD nitride film. In addition, after this, MO3LSI
If a gate oxide film is to be formed, the steps after forming the gate oxide film are continued as in the first embodiment.

The manufacturing method introduced in the embodiment is of course not limited to CMOS, and can also be applied to bipolar in addition to CMO3.

As described above, it was possible to obtain highly reliable elements and element isolation characteristics with extremely flat substrate surfaces.

〔Effect of the invention〕

According to the above configuration of the present invention, it is possible to obtain extremely flat element isolation on the substrate surface.
While the yield of good products was less than 2% for MO3, the average yield was 8%.
A yield as high as 0% was obtained.

Furthermore, whereas the combination of deep grooves and LOGO3 had a distance between wells of 4 μm or more, submicron separation was also possible.

As described above, highly reliable elements and element isolation characteristics could be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of essential parts showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIGS. 2(a) to 2(f) are process cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device of the present invention in order of process. FIGS. 3(a) to 3(d) are process cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device of the present invention in order of process. FIG. 4 is a sectional view of essential parts showing an example of a conventional method for manufacturing a semiconductor device. 1 ・ ・ 2 ・ ・ 3 ・ 4 ・ 5 ・ 6 ・ 7 ・ 8 ・ 9 ・ 10 ・ 11 ・ 12 ・ 13 ・ Semiconductor substrate Silicon oxide film Polycrystalline silicon photoresist CVD Silicon oxide film N- impurity layer P" impurity layer N''' Impurity layer P9 Impurity layer 1st wiring 2nd wiring CVD nitrided thermoplastic resin Applicant: Seiko Epson Corporation

Claims (1)

[Claims] (1) In a method for manufacturing a semiconductor device having two types of element isolation, including a deep groove and a shallow groove on a semiconductor substrate, and filling the two grooves, a) forming a deep groove, and filling more than half of the deep groove; 1. A method of manufacturing a semiconductor device, comprising the steps of: forming a shallow trench after filling; and b) simultaneously burying a remaining portion of the deep trench and a shallow trench.