JPH0223657A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize a large capacity condenser by forming a condenser section with a first electrode connected to a transistor, a second electrode disposed oppositely to the first electrode through a dielectric film, and a third electrode disposed oppositely to the second electrode through a dielectric film and connected to the first electrode. CONSTITUTION:In stacked memory cells, a second electrode 11 being a plate electrode as a common electrode among the memory cells includes first and third electrodes 8, 18 disposed on both sides thereof oppositely to each other through first and second dielectric films 10, 14. Accordingly, two capacitances are connected parallel to the second electrode 11. This assures that electric charges are stored not only on the one side of the second electrode but on both sides of the same. For this, capacity of the condenser section is increased. Thus, a larger capacity condenser section can be formed in the memory cells of limited areas.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a semiconductor memory device in which a plurality of memory cells each having a capacitor portion and a transistor are formed on a semiconductor substrate, and more specifically relates to a dynamic random access memory device. (hereinafter referred to as rDRAMJ) memory cell structure.

(Prior Art) In DRAMs, which are at the forefront of highly integrated semiconductor devices, the storage capacity has been increasing fourfold every three years.

Currently, IMb capacity products are commercially available, but in the future,
It is expected that the capacity will increase sequentially to 4Mb, 16Mb, and 64Mb.

Incidentally, in order to improve the degree of integration, it is necessary to reduce the area of a memory cell, which is a storage unit of a DRAM. However, in order to prevent soft errors caused by radiation and to ensure a signal with a sufficient S/N ratio, the charge storage capacity within the memory cell must be set to a certain minimum value or more.

Therefore, in a DRAM of 4 Mb or more, it is virtually impossible to form a capacitor section for storing charge on the surface of the semiconductor substrate. Therefore, the capacitor part
Memory cells with a so-called three-dimensional structure, which are formed inside holes or grooves (ie, trenches) formed in a semiconductor substrate or on MOS transistors formed on the surface of the substrate, are becoming more common.

(Problems to be Solved by the Invention) In a configuration in which a capacitor portion is formed inside a trench formed in a semiconductor substrate, it is possible to increase the capacitance depending on the depth of the hole or groove. Therefore, such a configuration can be said to be advantageous from the viewpoint of reducing the area of the memory cell.

However, it is technically very difficult to form relatively deep trenches with good reproducibility, and therefore, it is not necessarily an advantageous configuration from the viewpoint of mass production.

On the other hand, in the case of a so-called stacked memory cell in which the capacitor portion is formed on a MOS transistor, it is relatively easy to form the capacitor portion with good reproducibility. Therefore, in terms of productivity, this structure is more advantageous than the structure in which the capacitor portion is formed inside the trench.

However, it is difficult to increase the capacitance of the capacitor section compared to a structure using a trench.

Therefore, in the case of stacked memory cells, it is considered difficult to construct a highly integrated memory such as 16 Mb or 64 Mb.

Therefore, an object of the present invention is to provide a semiconductor memory device having a stacked memory cell with a capacitor structure that can be applied to a highly integrated DRAM such as a 64 Mb DRAM.

(Means for Solving the Problems) A semiconductor memory element of the present invention has a plurality of memory cells each having a capacitor portion and a transistor formed on a semiconductor substrate, and the capacitor portion partially connects the transistor. A semiconductor memory element formed to cover a first electrode electrically connected to one terminal of the transistor, and a first electrode formed on the first electrode. a dielectric film, a second electrode formed to face the first electrode via the first dielectric film, and a second dielectric film formed on the second electrode. and a third electrode formed to face the second electrode via the second dielectric film and electrically connected to the first electrode. The second electrode is used as a common wiring between the plurality of memory cells, thereby achieving the above object.

The semiconductor substrate used in the present invention may be p-type or n-type.
It is preferable to use a type Si substrate, and it is more preferable to use a p-type Si substrate.

Further, as the first dielectric film and the second dielectric film, for example, SiO2, Si, N, Ta201, or Ti
A film made of O, , or a composite film of these materials can be used. The first to third electrodes are preferably made of phosphorus or arsenic doped polycrystalline silicon, and the third electrode is made of W, Ta, Ti, AI, etc.
It is also possible to use metals such as or compounds and alloys of these and Si.

The film thickness of the first and second dielectric films in the present invention is such that the capacitance is 2X10-7F/cm" to 1X10-"F/cm.
It is desirable to set it within the range of 2. The thickness of the first electrode is preferably 0.5 to 1.5 μm, and the thickness of the second electrode is preferably 0.05 to 0.0 μm.
．． Preferably, the thickness is 2 μm.

(Function) According to the above configuration, in a so-called stacked memory cell, the first and second dielectric films are placed on both sides of the second electrode, which is a plate electrode serving as a common electrode between memory cells. 1st
, a third electrode is arranged facing each other. Therefore, the configuration is such that two capacitors are connected in parallel to the second electrode,
Since charges can be accumulated not only on one side of the second electrode but also on both sides, the capacitance of the capacitor section increases. Therefore, it is possible to form a capacitor portion with a larger capacity within a memory cell with a limited area.

(Example) The invention will now be described with reference to examples.

FIG. 1A is a plan view showing a portion of an embodiment of the present invention, and FIG. 1B (b) is a sectional view taken along line BB in FIG. 1A. This example concerns a memory cell applicable to a 64 Mb DRAM, and the unit memory cell is the first
1.8 μm x 1.2 μm surrounded by a dashed line in Figure A
It is configured within an area of size m. Functionally, this unit memory cell is composed of one N-channel transistor T and one capacitor section C.

The transistor T is conductive when the word line 4 is at a high level, and charges are exchanged between the bit line 22 and the capacitor section C, and a signal is written or read.

When word line 4 is at a low level, transistor T
becomes non-conductive, and the capacitor section C is separated from the bit line 22.

The transistor T has a p-type silicon substrate 1 as a channel, and a word line 4 serving as a gate electrode is formed on the channel with a gate insulating film 3 interposed therebetween. word line 4
is made of phosphorous-doped polycrystalline silicon. The drain region 6 of the transistor T connected to the bit line 22 and the source region 5 connected to the capacitor section C are constituted by an arsenic diffusion layer.

On the other hand, the capacitor section C is formed so as to partially cover the word line 4. That is, a first electrode 8 connected to the source region 5 of the transistor T, a second electrode 11 forming a plate electrode serving as a common wiring between a plurality of memory cells, and a third electrode 18. 5i02 film 10 as a first dielectric film and Sio2 film 1 as a second dielectric film
4 and more. The first to third electrodes 8.11.18 are
Both are made of phosphorus-doped crystalline silicon.

As is clear from FIGS. 1A and 1B, in this example, SiO2 is placed on both sides of the second electrode 11, which is a plate electrode.
Two films 10.14 are arranged, and two capacitors are formed between the first and third electrodes 8.18 and the second electrode 11, which are electrically connected to each other. has been done. Therefore, compared to conventional stacked memory cells of the same area,
It is possible to obtain larger capacity.

Next, an example of the manufacturing process of this embodiment will be explained with reference to FIGS. 2 to 6. In each figure, the figure numbered (b) is a sectional view taken along a line corresponding to line bb in FIG. 2(a). Further, since the transistor T portion can be manufactured using a conventionally known method and the same procedure, a description of the manufacturing process for this portion will be omitted.

2(a) and (b) respectively show the transistor T
FIG. 4 is a plan view and a cross-sectional view of a memory cell after forming a portion of FIG. Here, the so-called BOX method is adopted for element isolation. That is, a p-type Si substrate 1 has a depth of 0.6μ.
A trench of m is formed, boron is shallowly implanted into the side wall of the trench by ion implantation, and then a trench of 1 m is formed by thermal oxidation.
A 0.000000000000000000000000000000000000000000000000000000000000000in

Next, the process moves to the step of forming the gate insulating film 3 of the transistor T and the word line 4 which will serve as the gate electrode. Note that this embodiment employs a folded 1-bit line configuration. Further, as the material for forming the word line 4, polycrystalline silicon, polycide, high melting point metal, etc. can be used, but in this embodiment, phosphorus-doped polycrystalline silicon is used.

First, the polycrystalline silicon mask used as an etching stopper during planarization on the transistor region is removed.

Next, a 100-layer-thick gate insulator wA3 is formed by thermal oxidation. Furthermore, phosphorus-doped polycrystalline silicon was added to 0. 4
Deposited to μm thickness, followed by 0.

3 μm thick CVD-Si02 film (this is a Si film described later)
(2) which forms part of the film 7) is deposited. After processing this formed two-layer film into a word line pattern 4, phosphorus (P) was implanted at an energy of 30 keV (5 x 1013 cm-2) and O. A 1 μm thick LPCVD-SiO2 film was deposited, a gate electrode spacer (which becomes a part of the Si02 film 7) was formed by etching back, and arsenic was implanted at an energy of 60 keV (5 x 1015).
cm-2).

In the above process, LDD (Lightly
A source region 5 and a drain region 6 of a transistor T having a DopedDrain structure are formed.

Furthermore, an LPCVD-3i O2 film was deposited to a thickness of 1 μm, and an etch-back process was performed to remove 55% of the O2 film only on the side walls of the word line 4.
Leave the i02 membrane. The word line 4 is completely covered by this SiO2 film, the aforementioned gate electrode spacer Si○2 film, and the SiO2 film 7 made of the CVD-3in2 film, and at the same time, the openings above the source region 5 and drain region 6 are completely covered. A structure is obtained that is insulated from the

Next, the manufacturing process of the capacitor portion C will be explained.

First, phosphorus-doped polycrystalline silicon was deposited to a thickness of 1 μm, and R
By the IE method, a first electrode 8 connected to the source region 5 of the transistor T and an electrode 9 connected to the drain region 6 of the transistor T and later also connected to the bit line 22 are processed (FIG. 3(a)). and (b)).

Next, 6000 Si02MIO and 10a were formed by thermal oxidation method, and phosphorus-doped polycrystalline silicon was added to 0.1μ
It is deposited to a thickness of m. The phosphorus-doped polycrystalline silicon above the first electrode 8, that is, on the 5i02 film 10, which becomes the first dielectric film, is processed into the second electrode 11, which serves as a plate electrode.

At this time, since the electrode 9 is not covered with a mask, the phosphorus-doped polycrystalline silicon 12 remains only on its side wall. Further, on the first electrode 8, in order to connect the first electrode 8 and the third electrode 18, an opening 13 was provided in the second electrode 11 which becomes a plate electrode (see FIG. 4). a) and (b)).

Next, 70 SiO2 films 14 and 14a were formed by a thermal oxidation method, and 0.05 μm thick phosphorus-doped polycrystalline silicon 15 was deposited to form a part of the third electrode. Si○2 film 1
4 is the second dielectric film. In this example, the step of etching a part of the second dielectric film was not performed before depositing the phosphorus-doped polycrystalline silicon. The first electrode 8 and the third electrode 18 are not yet electrically connected. Therefore, the voltage 8i! on the first electrode 8 and the drain 6! Openings 16 and 17 were formed in the phosphorus-doped polycrystalline silicon 15 on the upper surface of the phosphorus-doped polycrystalline silicon 15 (FIGS. 5(a) and 5(b)).

Thereafter, 1° of the Si2 film in the openings 16 and 17 is removed by etching, and 0.05 μm thick phosphorus-doped polycrystalline silicon is deposited. This phosphorus-doped polycrystalline silicon and the above-mentioned phosphorus-doped polycrystalline silicon 15 are processed into one electrode connected to the third electrode 18 and the bit line 22, respectively. Through the above steps, the capacitor portion C can be formed (see FIGS. 6(a) and 6(b)).

Finally, the SiO2 film 2 is
A contact hole 21 for connecting the bit line 22 and the drain 6 of the transistor T is opened, and the AlSi alloy is etched by 0.5 ml.
It is deposited to a thickness of μm and processed into a bit line 22. As a result, the memory cell of the embodiment shown in FIGS. 1A and 1B[g is obtained.

In the memory cell formed by the above process, the area per memory cell is 1.8 x 1.2 μm2.16 μm2
, and the minimum dimension is 0.3 μm. The maximum aspect ratio of the pattern processed by the resist mask is 2.5.
It is relatively small and does not pose the difficulties of digging a deep trench.

Furthermore, the capacitance of the capacitor portion C of the memory cell of this example was 31 fF, which was a size that did not cause any practical problems. Also,
It was also confirmed that the retention time of accumulated charges is similar to that of conventional stacked memory cells.

(Effects of the Invention) As described above, according to the present invention, the first electrode covers a part of the transistor in the memory cell region and is connected to one terminal of the transistor; a second electrode arranged to face each other with a dielectric film in between, and a second electrode arranged to face the second electrode with a second dielectric film in between, and electrically connected to the first electrode; By forming a capacitor section with the connected third electrode, it becomes possible to realize a large capacity capacitor that could not be obtained with conventional stuffy memory cells. Therefore, a stacked unit memory cell with a cell area of around 2 μm2 can handle 64 Mb of DRA.
It is also possible to configure M.

As described above, the present invention provides a memory cell structure that is extremely useful for further increasing the storage capacity of DRAMs in the future.

,・ Day f Figure 1A is a plan view showing the main parts of an embodiment of the present invention;
Figure B is a sectional view taken along line B-B in Figure 1A, Figure 2(a)
2(b) to 6(a) and (b) are diagrams for explaining the manufacturing process of the example, respectively, FIG. 2(a) to 6(a) are plan views, and FIG. (b) to FIG. 6(b) are corresponding cross-sectional views taken along line bb in FIG. 2(a).

C...Capacitor section, T...Transistor, 1...
- p-type silicon substrate, 4... word line, 5... source region, 6... drain region, 8... first electrode,
10...SiO2 film (first dielectric film), 11...
Second electrode, 14...SiO2 film (second dielectric film)
, 15... Phosphorus-doped polycrystalline silicon film forming part of the third electrode, 18... Third electrode, 22... Bit line.

that's all

Claims (1)

[Claims] 1. A semiconductor memory in which a plurality of memory cells each having a capacitor part and a transistor are formed on a semiconductor substrate, and the capacitor part is formed to partially cover the transistor. An element in which the capacitor portion includes: a first electrode electrically connected to one terminal of the transistor; a first dielectric film formed on the first electrode; and a first dielectric film formed on the first electrode.
a second electrode formed to face the first electrode via a dielectric film; a second dielectric film formed on the second electrode;
The third electrode is formed to face the second electrode through a dielectric film, and is electrically connected to the first electrode, and the second electrode is A semiconductor memory element that is a common wiring between multiple memory cells.