JPH03230562A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To secure capacitor capacitance by increasing capacitance of a capacitance means by means of utilizing a side wall part of an insulating film formed on an upper part and a side wall of a gate electrode. CONSTITUTION:A memory cell 1 comprises an access transistor 21 and a capacitor 22. The capacitor 22 includes a lower electrode made of a conductive material such as polycrystal silicon, a dielectric layer 16 and an upper electrode 17. At this time the thickness of an insulating film 8a on a gate electrode 4a on the access transistor 21 is increased to form a lower electrode 15 of the capacitor 22 on the side wall and the upper part of the gate electrode. Therefore it is possible to increase a capacitor area by an amount of the increase in the thickness of the insulating film 8a. Thus the capacitor area can easily be increased without changing the area viewed from the plane, and sufficient capacitance can be secured even if the memory cell size is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular to a semiconductor device suitable for high integration that allows random manual output of arbitrary storage information and its manufacturing method. Regarding the manufacturing method.

[Background Art] In recent years, the demand for semiconductor devices has been rapidly expanding due to the remarkable spread of information devices such as computers. Furthermore, in terms of functionality, there is a demand for a device that has a large storage capacity and is capable of high-speed operation. Along with this, technological development regarding higher integration, high-speed response, and high reliability of semiconductor devices is progressing.

Among semiconductor devices, DRAM (Dynamic RAM) is one that can randomly input and output storage information.
ndom Access Memory) is known to the previous song. This DRAM is composed of a memory cell array, which is a storage area for storing a large amount of storage information, and peripheral circuits necessary for input/output with the outside.

FIG. 4 is a block diagram showing the configuration of a conventional DRAM. Referring to FIG. 4, a DRAM 50 includes a memory cell array 5 for accumulating data signals of storage information, and a row for externally receiving address signals for selecting memory cells constituting a unit memory circuit. AND column address buffer 52 and a row decoder 53 for specifying a memory cell by decoding its address signal.
and a column decoder 54, a sense refresh amplifier 55 that amplifies and reads out the signal stored in a designated memory cell, and a pig-in buffer 5 for data input/output.
6 and a data out buffer 57, and a clock generator 58 for generating a clock signal.

The memory cell array 51, which occupies a large area on a semiconductor chip, is formed by arranging a plurality of memory cells in a matrix for storing unit storage information.

FIG. 5 is an equivalent circuit diagram for explaining the configuration of a conventional memory cell array. Referring to FIG. 5, memory cell array 51 includes one MOS (Metal Oxygen
It consists of a transistor 21 and one capacitor 22 connected to it.
It is a capacitor type memory cell. This type of memory cell has a simple structure and is easy to improve the degree of integration of the memory cell array, and is widely used in large-capacity DRAMs.

Furthermore, DRAM memory cells can be divided into several types depending on their capacitor structure for storing signal charges.
There is a so-called stacked type memory cell disclosed in Japanese Patent No. 84.

FIG. 6 is a sectional view of a conventional stacked type memory cell described in the above-mentioned publication. Referring to FIG. 6, a stacked type memory cell includes a semiconductor substrate 1 and an impurity region 9 formed on the semiconductor substrate at a predetermined interval.
a, 9b, a gate electrode 4a located at the center of impurity regions 9a and 9b and formed through gate oxide film 3a, a lower electrode 11 of the capacitor directly connected to impurity region 9b, and a lower electrode 11 on lower electrode 11. dielectric layer 16 formed on
and an upper electrode 17 of a capacitor formed on the dielectric layer 16. A bit line 19b is connected to the upper electrode 17 via an insulating film 18, and the bit line 19a is also directly connected to the opening of the impurity layer 9a. In this type of memory cell, a capacitor is constructed from two layers of conductive films extending over word lines or element isolation regions and a dielectric film between them. Therefore, DRAM
When the memory cell size is reduced due to higher integration, the capacitor area is also reduced at the same time.

[Problems to be Solved by the Invention] As described above, when memory cells are reduced in size as DRAMs become more highly integrated, the area of capacitors is also reduced at the same time. However, DRA as a storage area
From the viewpoint of stable operation and reliability of M, it is necessary to maintain the amount of charge stored in a 1-bit memory cell almost constant even if the memory cell size is reduced. Possible means for this purpose include thinning the dielectric film of the capacitor and increasing the surface area by thickening the lower electrode of the capacitor. However, the method of making the dielectric film thinner has the problem of deteriorating the reliability of the dielectric film, and the method of increasing the surface area by making the lower electrode of the capacitor thicker has the problem of reducing the high level difference caused by increasing the thickness. There was a problem in that it was difficult to form a pattern for the dome electrode.

This invention was made to solve the above-mentioned problems, and it is possible to increase the capacitance of a stacked capacitor without the difficulty of patterning the lower electrode even when the memory cell size is reduced. An object of the present invention is to provide a semiconductor device suitable for high integration and a method for manufacturing the same, which can ensure high integration.

[Means for Solving the Problems] A semiconductor device according to the present invention includes at least two second conductivity type semiconductor substrates formed at a predetermined interval in a surface region surrounded by an element isolation region of a first conductivity type semiconductor substrate. an impurity region, a gate electrode formed on the semiconductor substrate between the two impurity regions via a first insulating film, and a second insulating film formed on the upper and sidewall portions of the gate electrode; A signal transmission line formed on one of the two impurity regions is connected to the other impurity region of the two impurity regions, and at least an end thereof is formed on the second insulating film. a capacitor having a first conductive film, at least a third insulating film formed on the first conductive film, and a second conductive film formed on the third insulating film; The capacitor means is characterized in that the capacitance is increased by utilizing the side wall portion of the second insulating film.

The method for manufacturing a semiconductor device according to the present invention includes the steps of forming an element isolation region on a semiconductor substrate of a first conductivity type, and forming a first insulating film on the main surface of the semiconductor substrate surrounded by the element isolation region. a step of forming a first conductive layer for forming a gate electrode on the first insulating film and on the element bone N region; forming a second insulating film on the first conductive layer;
In addition, the thickness of the second insulating film formed on at least the portion that will become the gate electrode is the same as that of the second insulating film formed on the element isolation region.
and forming at least two second insulating films in a region other than the region where the gate electrode is formed on the main surface of the semiconductor substrate surrounded by the element isolation region.
a step of forming a conductive type impurity region; a step of forming a first conductive film on one of the two impurity regions and on at least a sidewall portion of the second insulating film;
a step of forming a third insulating film on at least the first conductive film; a step of forming a second conductive film on the third insulating film; and a step of forming a third insulating film on at least the first conductive film; forming a signal transmission line.

[Function] In the semiconductor device according to the present invention, at least two impurity regions of the second conductivity type are formed at a predetermined interval in a surface region surrounded by the element isolation region of the semiconductor substrate of the first conductivity type. A gate electrode is formed on the semiconductor substrate between the two impurity regions via a first insulating film, a second insulating film is formed on the top and sidewall portions of the gate electrode, and one of the two impurity regions is A signal transmission line is formed on one impurity region, and a first conductive film is connected to the other impurity region and has at least an end formed on the second insulating film; A capacitive means is constituted by a third insulating film formed on the third insulating film and a second conductive film formed on the third insulating film, and the side wall portion of the second insulating film is utilized by the capacitive means. Since the capacitance is increased by increasing the capacitance, the area that can be used as the capacitor means is increased without increasing the area on the plane, and there is no need to increase the thickness of the first conductive film serving as the lower electrode of the capacitor means.

In the method for manufacturing a semiconductor device according to the present invention, an element isolation region is formed on a semiconductor substrate of a first conductivity type, and a first insulating film is formed on the main surface of the semiconductor substrate surrounded by the element isolation region. , a first conductive layer for forming a gate electrode is formed on the first insulating film and the element isolation region, a second insulating film is formed on the first conductive layer, and at least The thickness of the second insulating film formed on the portion that will become the gate electrode is thicker than the thickness of the second insulating film formed on the element isolation region, and the second insulating film is surrounded by the element isolation region. At least two impurity regions of the second conductivity type are formed in a region other than the region where the gate electrode is formed on the main surface of the semiconductor substrate, and on one of the two formed impurity regions and A conductive film is formed on at least the sidewall portion of the second insulating film, a third insulating film is formed on at least the first conductive film, and a second conductive film is formed on the third insulating film. A signal transmission line is formed on the other of the two impurity regions. In other words, the second insulating film formed on at least the portion that will become the gate electrode is formed so that it is thicker than the second insulating film formed on the element isolation region, and the gate electrode Since the first conductive film is formed on at least the sidewall portion of the second insulating film formed on the portion that will become the gate electrode, the thickness of the second insulating film formed on the portion that will become the gate electrode is increased. The area that can be used as the capacitor means is increased without increasing the area on the plane, and there is no need to increase the thickness of the first conductive film serving as the lower electrode of the capacitor means.

[Embodiment of the Invention] FIG. 1A is a cross-sectional structural diagram of a stacked type memory cell of a DRAM according to an embodiment of the present invention. FIG. 1B is a plan layout diagram of the memory cell shown in FIG. 1A. Referring to FIGS. 1A and 1B, the memory cell is composed of one access transistor 21 and one capacitor 22. This memory cell is insulated and isolated from adjacent memory cells by an element isolation region 2 formed on the surface of a semiconductor substrate 1.

The access transistor 21 includes impurity regions 6a, 9a, and 6b9b formed on the surface of the semiconductor substrate 1, and a gate electrode 4a located between the impurity regions 6a, 9a, and 6b9b through a thin gate oxide film 3. including.

The capacitor 22 includes a lower electrode 15 made of a conductive material such as polycrystalline silicon, a dielectric layer 16 formed on the lower electrode 15 and made of a dielectric material such as a laminated film of a nitride film and an oxide film or a tantalum oxide film, and an upper electrode 17 made of a conductive material such as polycrystalline silicon formed on the dielectric layer 16.

The lower electrode 15 is connected to the source or drain region 6b, 9b of the access transistor 21. The bit line 19b is formed on an interlayer film made of the insulating film 18, and is directly connected to the source or drain region 6a, 9a of the access transistor 21 or in a conductive layer (bit line).
19a.

Further, the thickness of the insulating film 8a on the gate electrode 4a of the access transistor 21 is increased, and the lower electrode 11 of the capacitor 22 is formed on the sidewall portion and upper part thereof. This makes it possible to increase the area of the capacitor by the increased thickness of the insulating film 8a.

Therefore, the capacitor area can be easily increased without changing the capacitor area without changing the area seen from a plane, and a sufficient capacity can be ensured even if the memory cell size is reduced. Note that a gate electrode 4b is also formed on the element isolation region 2, and an insulating film 8b is formed on the gate electrode 4b. An insulating film 10 made of a nitride film is formed on the right side of the insulating film 8b, and a lower electrode 11 of the capacitor 22 is formed on a part of the nitride film 10 and on the insulating film 8b.

FIGS. 2A to 2N are cross-sectional structural views for explaining the manufacturing process of the memory cell shown in FIG. 1A.

The manufacturing process will be described with reference to FIGS. 2A to 2N. First, as shown in FIG. 2A, an element isolation region 2 is formed in a predetermined region of the surface of the semiconductor substrate 1 using the LOCO3 method. Next, as shown in FIG. 2B, the surface of the semiconductor substrate 1 is thermally oxidized to form an oxide film 3 on the surface of the semiconductor substrate 1 surrounded by the element isolation region 2. Low pressure CVD
A conductive film 4 of polycrystalline silicon doped with phosphorus is formed by
is formed on the oxide film 3, and further, an insulating film 5 made of an oxide film is formed using a low pressure CVD method so that the part corresponding to the upper part of the oxide film 3 is thicker than the part corresponding to the upper part of the element isolation region 2. Form it so that it is thick. The entire surface of the insulating film 5 is etched by isotropic etching such as wet etching or dry etching to obtain the insulating film 5 of a required thickness.

As shown in FIG. 2C, the oxide film 3 is etched using photolithography and dry etching. The conductive film 4 and the insulating film 5 are removed except for predetermined portions.

As a result, gate oxide film 3 and gate electrodes 4a and 4b of the access transistor and word line are formed.

Next, as shown in FIG. 2D, using the gate electrodes 4a, 4b and the insulating films 5a, 5b formed on them as masks, a relatively low concentration of impurities is implanted into the surface of the semiconductor substrate 1 by ion implantation. Regions 6a and 6b are formed. As shown in FIG. 2E, an insulating film 7 made of an oxide film is formed over the entire surface of the semiconductor substrate 1 by low pressure CVD. Next, the 2nd F
As shown in the figure, the insulating film 7 is etched by anisotropic etching.
is selectively removed to form insulating films 8a and 8b on the upper and sidewall portions of gate electrodes 4a and 4b. Next, as shown in FIG. 2G, using the gate electrodes 4a, 4b and the insulating films 8a, 8b above them as masks, a relatively high concentration impurity region 9 is implanted into the surface of the semiconductor substrate 1 by ion implantation.
a, 9b are formed. As a result, a transistor having a so-called LDD structure is formed, but the structure of the access transistor does not have to be an LDD structure, and may have another structure. Next, as shown in FIG. 2H, an insulating film 10 made of a nitride film is formed on the semiconductor substrate 1 by low-pressure CVD, and then the lower electrode of the capacitor is connected using ordinary photolithography and etching. Then, the nitride film 10 in the source/drain regions 6b and 9b is selectively removed. Next, as shown in FIG. 21, low pressure CVD
A conductive film 11 made of polycrystalline silicon is formed on the entire surface of the semiconductor substrate 1 by a method, and source/drain regions 6b, 6 are formed using a normal photolithography method and an etching method.
The conductive film 11 is selectively removed except for portions b and extending to the nitride film 10. Next, as shown in FIG. 2J, after an insulating film 12 made of an oxide film is formed on the entire surface of the semiconductor substrate l by the CVD method, an opening 13 in which the conductive film 11 resides is formed. Next, as shown in the figure, a conductive film 14 made of polycrystalline silicon is formed by low pressure CVD.
is formed on the entire surface. Next, as shown in FIG. 2L, the conductive film 14 on the insulating film 12 is removed by anisotropic etching. As a result, a square columnar conductive film remains on the side wall of the opening 13, and together with the conductive film 11, the lower electrode 15 of the capacitor is formed. As shown in FIG. 2M, the insulating film 1
After removing 2, a nitride film is formed on the entire surface of the semiconductor substrate 1 by low pressure CVD method, and the semiconductor substrate 1 is heat-treated in an oxygen atmosphere. As a result, a portion of the nitride film is oxidized to form the dielectric film 16 of the capacitor.

Conductive film 1 made of polycrystalline silicon is formed by low pressure CVD method.
7 is formed on the entire surface of the semiconductor substrate 1. Then, portions other than those forming the capacitor 22 are removed. Next, the second
As shown in Figure N, an insulating film 18 made of an oxide film is formed over the entire surface of the semiconductor substrate 1 by the CVD method. bit line 1
The insulating film 18 at the connection portion between the access transistor 9a and the source-drain regions 6a, 9a of the access transistor is selectively removed by ordinary photolithography and etching. Next, a tungsten film 19a is selectively formed in the opening of the insulating film 18 by the CVD method, and the opening is filled with the tungsten film 19a.

Furthermore, a conductive film made of tungsten silicide is deposited over the entire surface using a sputtering method. Thereafter, the bit line 19b is formed by patterning into a predetermined shape using ordinary photolithography and etching methods.

Note that in this embodiment, a tungsten silicide film is shown as the bit line 19a, but the present invention is not limited to this.
Polycrystalline silicon film, metal silicide film, metal film, TiN
It may be a membrane or a composite membrane in which these membranes are stacked alternately. Further, although a tungsten silicide film formed by sputtering is shown as the bit line 19b, the present invention is not limited to this, and the present invention is not limited to this. It may also be a composite membrane layered on top of each other. Further, in this embodiment, the bit line 19b is connected to the source train regions 6a, 9a of the access transistors via the bit line 19a, but the present invention is not limited to this.
The bit line 19b is directly connected to the source train region 6a via the bit line 9a.

It may be connected to 9a. In addition, in this embodiment, as a method for forming the insulating films 5a and 5b, after forming the thick insulating film 5, isotropic etching such as wet etching or dry etching is performed to achieve the required film thickness, and then photolithography and dry etching are performed. Although an example in which the gate electrode is formed using an etching method is shown, the present invention is not limited to this, and the present invention is not limited to this. It may also be formed using a dry etching method. Furthermore, when forming the insulating films 5a and 5b, the required film thickness may be deposited as is. Further, in this embodiment, the shape of the lower electrode of the capacitor is formed into a rectangular prism shape as shown in FIG. can get.

Further, in this embodiment, an example of the LOCO5 method is shown in which a thick oxide film is formed in the element isolation region, but the present invention is not limited to this, and the same effect can be obtained by using other isolation methods, such as the field shield method. is obtained.

FIG. 3 is a cross-sectional structural diagram of a DRAM memory cell showing a second embodiment of the present invention. Referring to Figure 3,
The difference from the embodiment shown in FIG. A is that the lower electrode of the capacitor does not have a rectangular columnar electrode portion, but is constructed by spanning one lower electrode. This also provides the same effect as the first embodiment shown in FIG. 1A.

[Effects of the Invention] According to the invention described in the first claim, the capacitance of the capacitor means is increased by using the side wall portion of the second insulating film formed on the upper and side wall portions of the gate electrode. This increases the area that can be used as a capacitor without increasing the planar area, and there is no need to increase the thickness of the first conductive film that serves as the lower electrode of the capacitor. It has now become possible to provide a semiconductor device suitable for high integration, which can ensure capacitor capacity without any difficulty in patterning the lower electrode even when the size is reduced.

According to the second aspect of the invention, the thickness of the second insulating film formed on at least the portion that will become the gate electrode is made thicker than the thickness of the second insulating film formed on the element isolation region. By forming the first conductive film on at least the side wall portion of the second insulating film formed on the portion that will become the gate electrode, the capacitive means can be formed without increasing the planar area. Since the area available for use as a capacitor is increased and there is no need to increase the thickness of the first conductive film, which serves as the lower electrode of the capacitor, patterning of the lower electrode becomes easier even when the memory cell size is reduced in a stacked capacitor. It has now been possible to provide a method of manufacturing a semiconductor device suitable for high integration, which can ensure capacitor capacity without the above-mentioned difficulties.

[Brief explanation of drawings]

FIG. 1A is a sectional view of a DRAM memory cell showing an embodiment of the present invention, FIG. 1B is a plan layout diagram of the memory cell shown in FIG. 1A, and FIGS.
A cross-sectional structural diagram for explaining the manufacturing process of the DRAM memory cell shown in the figure, FIG. 3 is a cross-sectional diagram of a memory cell showing a second embodiment of the present invention, and FIG. 4 is a conventional DRAM
5 is an equivalent circuit diagram for explaining the configuration of a conventional memory cell, and FIG. 6 is a sectional view of a conventional stacked type memory cell. In the figure, 1 is a semiconductor substrate, 2 is an element isolation region, 3 is a gate oxide film, 4a, 4b are gate electrodes, 6a, 6b are impurity regions, 8a, 8b are insulating films, 9a, 9b are impurity regions, 11, 1.5 is a lower electrode,] 6 is a dielectric film, 17 is an upper electrode, 18 is an insulating film, 19a and 19b are bit lines,
21 is an access transistor, and 22 is a capacitor. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] (1) at least two impurity regions of a second conductivity type formed at a predetermined interval in a surface region surrounded by an element isolation region of a semiconductor substrate of a first conductivity type, and the impurity regions between the two impurity regions. a gate electrode formed on a semiconductor substrate via a first insulating film; a second insulating film formed on the upper and sidewall portions of the gate electrode; and one impurity region of the two impurity regions. a signal transmission line formed on the second insulating film; and a first conductive film connected to the other of the two impurity regions and having at least an end thereof formed on the second insulating film. capacitor means having a third insulating film formed on the first conductive film and a second conductive film formed on the third insulating film, the capacitor means having a third insulating film formed on the first conductive film; A semiconductor device characterized in that a side wall portion of an insulating film is used to increase its capacitance. (2) forming an element isolation region on a semiconductor substrate of a first conductivity type; forming a first insulating film on the main surface of the semiconductor substrate surrounded by the element isolation region; forming a first conductive layer for forming a gate electrode on the first insulating film and on the element isolation region; forming a second insulating film on the first conductive layer; forming the second insulating film formed on the portion that will become the gate electrode so that it is thicker than the second insulating film formed on the element isolation region; forming at least two impurity regions of a second conductivity type in a region other than the region where the gate electrode is formed on the main surface of the semiconductor substrate surrounded by an element isolation region; forming a first conductive film on one of the impurity regions and on at least a sidewall portion of the second insulating film; forming a third insulating film on at least the first conductive film; A method for manufacturing a semiconductor device, comprising: forming a second conductive film on the third insulating film; and forming a signal transmission line on the other of the two impurity regions.