JPH02236594A - Sampling clock generating circuit for video signal - Google Patents

Abstract

PURPOSE:To widely operate a variable range by a video signal by using a PLL circuit in which a voltage control oscillator VCO is contained, providing a frequency converting circuit on its output and setting an oscillation frequency of the VCO higher than a necessary frequency. CONSTITUTION:At the time of controlling a PLL circuit by using the PLL circuit in which a VCO 1 is contained and using a horizontal synchronizing signal of a video signal or a composite synchronizing signal, an output of the VCO 1 is inputted to a double balanced modulator DBM. That is, by providing the DBM on an output side of the VCO 1, and an oscillation frequency of the VCO 1 is set higher than a necessary frequency. In such a way, the video signal can be varied extending over a wide range, and complicated circuits can be collected to one.

Description

Detailed Description of the Invention [Industrial Application Field 1] The present invention relates to a sampling clock generation circuit for accurately and widely sampling data of each pixel included in a video signal in a recording device. It is. [Summary of the Invention] The present invention provides sample data for each pixel based on a video signal in a recording device. A PLL circuit with a built-in VCO is used in the clock generation circuit for
A frequency conversion circuit is provided at the output of the VCO, and the oscillation frequency of the CO is set higher than the required frequency, making it possible to operate the VCO over a wide variable range of oscillation frequency. [Conventional technology 1 Recent CAD. Image display devices for CAM applications are becoming increasingly high-definition and high-resolution. On the other hand, in the lower resolution range, some devices use general personal computers, and the recording devices used in these devices also require a wide range of specifications. In a recording device that uses video signals as a medium, there is a one-to-one response to this video frequency.
Data must be sampled with a sampling clock corresponding to several MH. Requires a sampling clock with a very wide range of ~100-odd MHz. For this reason, conventional clock generation circuits have two VCOs, one for the low band and one for the high band, or have a narrow sampling range. They also responded to requests for high-end machines for low-frequency and high-frequency use.

[Problem to be Solved by the Invention 1] However, in the above-mentioned method, a complicated PLL. Its specifications were limited by the provision of dual VCO circuits. Again 1
When the frequency is varied over a wide range with one VCO, the variable amount will be the same value as the VCO's lower frequency limit (variable up to twice the frequency), and beyond that, the variable amount will be too large. The operation became unstable and was not at a practical level. 1,000 Steps to Solve the Problem 1 In order to solve the above problems, this invention provides a generally known DBM on the output side of the VCO, and sets the oscillation frequency of the VCO higher than the required frequency. This allows the frequency variable range to be widened. This resulted in a circuit configuration that uses DBM to convert to the desired frequency. Control to the PLL is performed using the converted output of the DBM. [Effect 1] The video signal configured as described above can be varied over a wide range, complex circuits can be integrated into one, and reliability is improved. Also, the amount of frequency variation of the VCO is relatively small because the oscillation frequency of the VCO is high.
The oscillation voltage also changes little within the variable range, resulting in stable operation.

[Embodiment 1] An embodiment of this invention will be explained below based on the drawings. 1st
The figure shows a block diagram outlining the present invention. VCOL
is selected as the target frequency f3 and oscillates at a frequency higher than f4 oscillated by OSC2. That is, f +
= f i + f 4. D. BM3 mixes f and f4 inputted by a double balance mixer, and outputs f++f4 and f1-f. Outputs f, which has two frequency components. At this time, n times f1, n times f4, and f. ．． f. Since the object is a balanced type, only two frequency components are generated in the output. The next LPF4 is f of the components of f2.
．． It is a low-pass filter so that only -f4 is selected, and the output f, is f. -f. Only the frequency components of will come out. Based on this f, feedback is applied to the VCO 1 through a frequency divider 5, a position shift comparator 6, etc. in the same way as in a general PLL circuit. Figure 2 is a spectrum showing the spurious components included in f. LPF4
The cut frequency is set so that only f3 appears in the output. The variable range Δf to be obtained can be selected from the frequency f1 of vcot. Δf with respect to f is a variable range that can be sufficiently covered by an oscillation circuit, and in the conventional case where the frequency of f was directly oscillated, the magnitude of Δf with respect to f was large and unstable. The vco t of this invention is f1
Since it oscillates at a higher frequency by the frequency of f, the relative amount of variation is small. [Effects of the invention I Since the oscillation frequency of VCO 1 is set to a desired frequency, the variable range in the oscillation circuit is relatively small.
Therefore, the oscillation voltage etc. are made uniform.

Additionally, element variations and fluctuations are reduced, improving reliability and stability. In addition, if the target frequency is directly oscillated, the variable range can be widened by selecting 1 or 2, so that the required specifications can be satisfied with one VCO.

[Brief explanation of drawings]

Figure 1 is a block diagram of the present invention. Figure 2 is a spectrum showing the oscillation frequency. l ・ ・ ・ V-C O 2・・・・OSC 3・・・・DBM ・LPF ・Frequency divider ・Position comparison Below Up

Claims (1)

[Scope of Claims] 1) In a recording device that inputs a video signal for displaying image data on a display device and records the image data, a PLL circuit having a built-in VCO (voltage controlled oscillator) is used to generate the video signal. A video signal sampling clock generation circuit characterized in that the output of a VCO is once converted to another frequency and then the converted value is used when controlling the PLL circuit using a horizontal synchronization signal or a composite synchronization signal. 2) The video signal sampling clock generation circuit according to claim 1, wherein the output of the VCO is input to a DBM (double balanced modulator).