JPH02236725A - Information processor - Google Patents

Abstract

PURPOSE:To measure the number of steps of an execution instruction correctly by setting a register simultaneously with the start of the execution of an instruction program to realize a second class instruction, and resetting the register when an instruction representing the completion of the execution of the instruction program is executed. CONSTITUTION:The title device is constituted of a main storage 1, an instruction fetch circuit 2, a memory 3 for instruction analysis, a control memory circuit 4, a step counter 5, and the register 6. The register 6 is set to '1' simultaneously with the start of the execution of the instruction program to realize the second class instruction, and is reset to '0' when the instruction Ad representing the completion of the execution of the instruction program is executed. Since the register 6 holds '1' while the instruction program is executed, no count-up of the step counter 5 is performed even when a decode signal (d) goes to '1'. Thereby, it is possible to count the number of steps of a software instruction at every execution of the final step of the instruction program to realize the second class instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device controlled by a microprogram.

[Conventional technology]

Conventionally, in order to improve processing performance, this type of information processing device has a so-called horizontal processor with a large bit configuration, in which the microinstructions that make up the microprogram execute more functions in one step to improve parallel processing performance. The shift to type microinstructions is noticeable.

In particular, for frequently used instructions such as basic arithmetic instructions, the hardware structure is optimized to take full advantage of the features of the horizontal microinstructions mentioned above, so the number of microprogram steps is extremely small. Ru.

However, many other instructions, such as various control instructions and list processing instructions that repeat data operations in main memory, often involve sequential processing (a highly horizontal microprocessor is required for such functions). Even if you use the command
Since the degree of parallelism of the functions executed in l steps is not high, there are many unused fields of microinstructions, which has the disadvantage that the word-wise utilization of the control memory that stores the microprograms is poor. To overcome this drawback,
A method is adopted in which various other control instructions are realized by an instruction program consisting of basic operation instructions realized by a microprogram. An information processing apparatus using this method will be explained with reference to FIG. The information processing device shown in FIG.
) It consists of 5. The main memory 1 includes a software program storage section 11 that performs predetermined processing, and a plurality of instruction program group storage sections 12 that are written using first type instructions.

A microprogram is stored in the control memory circuit 4, and a microinstruction register (RD) 4 is stored from the control memory 4l.
The signal obtained by decoding the microinstruction read out in step 4 by the decoder 45 controls various arithmetic processing in order to realize the function defined by the first type of instruction.

The software program in the storage section 11 on the main memory 1 is read out from the main memory 1 according to the address indicated in the instruction address register (JAR) 21 and stored in the instruction buffer register (IBR) 22. The fetching of an instruction is called prefetching, and is generally fetched in advance so that the instruction has already arrived at the instruction buffer register 22 by the time the instruction is actually executed.

First, the first type of instructions, that is, the instructions implemented by the microprogram on the control memory 41, will be explained. The first type of instruction is a basic instruction that can fully take advantage of the parallel processing effect of horizontal microinstructions, and is generally used much more frequently in software programs. The instruction code section 222 of the instruction stored in the instruction buffer register 22 is supplied to the instruction analysis memory 3, from which information a, b, and c are read out as initial values necessary for microprogram control of the processing of the corresponding instruction. It's coming.

Information b is information indicating whether this instruction is type 1 or type 2, and is information that indicates whether this instruction is type 1 or type 2.
2. If it is the first type of instruction, the microinstruction sequencer (SEQ) 42 reads the control memory 41 using information a as the starting address of the microprogram that implements the processing of the instruction, and the read microinstruction is temporarily After being stored in the microinstruction register 44, it is supplied to the decoder 45. The calculation is controlled by the output signal d decoded by the decoder 45.

Note that the microinstruction stored in the microinstruction register 44 includes information on how to determine the address from which to read the next microinstruction or information on the address itself, and this is supplied to the microinstruction sequencer 42 to read the next microinstruction. The target microprogram is then executed sequentially.

Next, instructions realized by a software program consisting of the second type of instructions, that is, the first type of instructions, will be explained. When the second type of instruction is attempted to be realized by a microprogram, the parallel processing effect of the horizontal type microinstruction cannot be exhibited as much, and the usage is rather similar to that of the vertical type microinstruction.

When the output information b of the instruction analysis memory 3 informs the microinstruction sequencer (SEQ) 42 that it is a second type instruction, the reading of the microinstruction from the control memory 41 to the microinstruction register 44 is stopped. A no-operation (NOP) microinstruction is stored in the microinstruction register 44, and the arithmetic operation is temporarily suspended. At the same time, information b is provided to the branch address generation circuit 23, and if it is a second type instruction, information C is stored in the instruction address register 21 as the start address of the instruction program that processes the instruction, and at the same time this address is starts the operation of reading an instruction from the instruction program group in the storage section l2 of the main memory 1, and the first instruction of this instruction program is stored in the instruction buffer register 22. Furthermore, information b instructs to store the value of the instruction counter 25 (instruction address) of the first type 2 instruction into the instruction counter standby register (ICR) 26.

Here, the first type and second type instructions will be explained using FIG. In this figure, the first type of instruction is shown as An, and the second type of instruction is shown as Bn. In the explanation so far, the first instruction Aa of the instruction program Aa-Ab-eAc→Ad for executing the second type instruction B1 is stored in the instruction buffer register 22. Since Aa is a type 1 instruction, it is realized by the microprogram in the control memory 41 as described above with reference to FIG. The same applies to Ab-*Ac below.

Although Ad is a first type instruction, it is the last instruction of the instruction program for realizing the second type instruction B1, and is the next instruction A of 81 on the original software program sequence.
It plays a role in returning to 3.

Here, the operation of instruction Ad will be explained with reference to FIG. 3 again. Instruction Ad is defined as a relative branch instruction based on the address stored in the instruction counter save register 26. Since the instruction counter value of instruction B1 in FIG. 2 is stored in the instruction counter save register 26, by setting the instruction word length of instruction B1 as the displacement of the relative branch instruction, the instruction The instruction address of the next instruction after instruction 81 in the sequence, that is, instruction A3, is generated and stored in the instruction address register 21, and at the same time, this address starts the operation of reading the instruction from the software program storage section 11 of the main memory 1, and this instruction is stored in the instruction buffer register 22. Since A3 is the first type of instruction, it is realized by the microprogram on the control memory 41 as described above, and the instructions on the software program are subsequently executed sequentially.

By the way, as an index for evaluating the performance of an information processing device,
The number of instructions executed per unit time is widely used. The number of instructions executed per unit time is theoretically determined as the reciprocal of the sum of the time required to execute each instruction multiplied by the frequency of occurrence of that instruction (i.e., the average instruction execution time), but in reality, the number of instructions executed per unit time It is difficult to estimate the frequency, and it is also necessary to estimate parameters such as the probability that an instruction or operand exists in the cache memory.

Therefore, instead of calculating the number of instructions executed per unit time by theoretically calculating the average instruction execution time as described above, a method of actually measuring the number of instructions executed per unit time is used. In this method, a means for measuring the number of executed instruction steps, such as a counter called a step counter that increments or subtracts by 1 each time a software instruction is executed, is provided, and this step counter is measured in real time measured by a timer. Find the number of instructions executed per unit time by dividing the value of .

The stamp counter 5 in Figure 3 corresponds to this. A step counter update microinstruction is always written in the last step of a microinstruction program for implementing a type 1 instruction. When the step counter update microinstruction is read from the control memory 41 to the microinstruction register 44 when executing the last step of the microinstruction program for realizing a type 1 instruction, its contents are decoded by the decoder 45. , the decoded signal d is rl
Become J. Since the decode signal d becomes rlJ, the step counter 5 counts up by one. As described above, the step counter 5 increments one count each time the last step of the microinstruction program for implementing a type 1 instruction is executed, and the number of steps of the executed software instruction can be measured.

In FIG. 3, 43 is a micro address register.

[Problem to be solved by the invention]

In an information processing device that realizes a second type of instruction by an instruction program configured with first type of instructions, the first type of instruction, the second type of instruction,
Regardless of the type of instruction, the step counter 5 must be updated by 1 every time one instruction is executed. However,
In conventional devices, during the execution of an instruction program, the step counter is updated unnecessarily as the type 1 instructions that make up the instruction program are executed, so there has been a problem that the number of executed instruction steps cannot be accurately measured. .

[Means to solve the problem]

In order to solve such problems, the present invention provides first type instructions realized by a microprogram on a control memory, and second type instructions realized by an instruction program composed of the first type instructions. A register that is set at the start of an instruction program to implement the second type of instruction and reset at the end of the instruction program, and a register that stores the software instruction 1 only when this register is in the reset state. An instruction counting means is provided which adds or subtracts one each time a step is executed.

[Effect]

The information processing device according to the present invention sets the register at the same time as the execution of the instruction program for realizing the second type of instruction starts, and resets the register at the time of execution of the instruction indicating the end of the instruction program execution.

〔Example〕

FIG. 1 is a system diagram showing an embodiment of an information processing apparatus according to the present invention. This embodiment is composed of a main memory 1, an instruction fetch circuit 2, an instruction analysis memory 3, a control memory circuit 4, a stump counter 5, and a register 6. are given the same reference numerals.

First, the first type of instructions, that is, the instructions implemented by the microprogram on the control memory 41, will be explained. The first type of instructions are basic instructions that can fully take advantage of the parallel processing effect of horizontal microinstructions, and are generally used much more frequently in software programs. The instruction code part 222 of the instruction stored in the instruction buffer register 22 is supplied to the instruction analysis memory 3, and information a, b, and c are read from there as initial values necessary for microprogram control of the processing of the corresponding instruction. come.

Information b becomes “0” when this instruction is the first type, and
This information is “1” when the instruction is a seed, and is provided to the microinstruction sequencer 42. If the instruction is of the first type, the microinstruction sequencer 42 stores information a in the control memory 41 as the starting address of the microprogram that implements the processing of the instruction.
The read microinstructions are once stored in the microinstruction register 44 and then provided to each arithmetic circuit. Note that this microinstruction includes information on the address itself or how to determine the address from which to read the next instruction microinstruction, and this is supplied to the microinstruction sequencer 42 to read out the next microinstruction, and thereafter sequentially. Executes the desired microprogram.

Next, instructions realized by a software program consisting of the second type of instructions, that is, the first type of instructions, will be explained. When the second type of instruction is realized by a microprogram, the parallel processing effect of the horizontal microinstruction cannot be exhibited as much, and the usage is rather similar to that of the vertical microinstruction.

When the output information b of the instruction analysis memory 3 informs the microinstruction sequencer 42 that it is a second type instruction, the reading of the microinstruction from the control memory 41 to the microinstruction register 44 is stopped, and the microinstruction register 44 stops reading the microinstruction from the control memory 41.
4 stores a no-operation (NOP) microinstruction, and the arithmetic operation controlled by the microinstruction is temporarily suspended. At the same time, information b is provided to the branch address generation circuit 23, and if it is a second type instruction, information C is provided.
is stored in the instruction address register 21 as the start address of the instruction program that processes the instruction, and at the same time, the instruction program group storage division 12 of the main memory 1 is stored using this address.
The first instruction of this instruction program is stored in the instruction buffer register 22.
Further, information b instructs to store the value of the instruction counter 25 (instruction address) of the first type 2 instruction in the instruction counter save register 26, and sets the register 6 to "1".

Here, using Figure 2, type 1. The second type of command will be explained. In this figure, the first type of instruction is shown as An, and the second type of instruction is shown as Bn. In the explanation so far, the first instruction Aa of the instruction program A a -* A b -* A c-Ad for executing this is stored in the instruction buffer 22 by the second type of instruction B1. Become. Since Aa is a type 1 instruction, it is realized by the microprogram in the control memory 41 as described above with reference to FIG. The same applies to Ab-+Ac below. Although Ad is a first type instruction, it is the last instruction of the instruction program for realizing the second type instruction B1, and plays the role of returning to the next instruction A3 of 81 on the original software program sequence. Fulfill.

Here, the operation of the instruction Ad will be explained with reference to FIG. 1 again. Instruction Ad is defined as a relative branch instruction based on the address stored in the instruction counter save register 26. First, the register 6 is reset to "0" by the output C of the instruction analysis memory 3. Since Ad is the first type of memory, the instruction counter save register 2 is saved by the microprogram on the control memory 4l as explained earlier.
The instruction counter value of instruction B1 in FIG. 2, which is held at 6, is
By adding the instruction word length of instruction B1 as the displacement of the relative branch instruction, the branch address generation circuit 23 calculates the instruction next to instruction B1 in the instruction sequence, that is, instruction A.
3 instruction addresses are generated. The generated instruction address is stored in the instruction address register 21, and at the same time, this address starts the operation of reading an instruction from the software program storage section 11 of the main memory 1, and this instruction is stored in the instruction buffer register 22. The instructions on the software program are then executed sequentially. In this embodiment, the register 6 is reset by the output of the instruction analysis memory 3, but the present invention is not limited to this, and the register 6 may be reset by, for example, a microinstruction. In the above explanation, register 6 is set to rlJ at the same time as the execution of the instruction program for implementing the second type of instruction starts, and register 6 is reset to rOJ when the instruction Ad indicating the end of execution of the instruction program is executed. except for the third
This is exactly the same as the explanation for the conventional device shown in the figure. Here, how the step counter 5 is updated in this embodiment will be explained. First, updating of the step counter 5 when the instruction program for realizing the second type of instruction is not executed will be explained. Be sure to write the step counter update microinstruction in advance in the last step of the microinstruction program to implement the type 1 instruction. When the stump counter update microinstruction is read from the control memory 41 to the microinstruction register 44 when executing the last step of the microinstruction program for realizing a type 1 instruction, its contents are transferred to the decoder 45.
The decoded signal d becomes "1".

The AND signal of the decode signal d and the negation of the value held in the register 6 serves as the count amplifier signal of the step counter 5. When the instruction program is not executed, register 6 holds rOJ, so the decode signal is "1".
”, the step counter 5 increments by one. As described above, the step counter 5 counts up by 1 each time the last step of the microinstruction program for realizing a type 1 instruction is executed, and the number of executed software instruction steps can be measured. .

Next, updating of the step counter 5 when executing the second type of instruction will be explained. As already explained, register 6 is set to "1" by execution of the second type of instruction, and branching to the instruction program is performed. During execution of the instruction program, the first
When the last step of the microinstruction program of the seed instruction is executed, the step counter update microinstruction is read from the control memory 41 to the microinstruction register 44, its contents are decoded by the decoder 45, and the decode signal d becomes "1". Become. An AND signal of the decode signal d and the negation of the value held in the register 6 is output to the step counter 50.
This is a count up signal. Since the register 6 holds "1" while the instruction program is being executed, the step counter 5 does not count up even if the decode signal d becomes "1". As described above, it is possible to prevent the step counter 6 from counting up during the execution of the instruction program for realizing the second type instruction.

As already explained, when the instruction program ends, the register 6 is reset by the last instruction of the instruction program, and the original software program is returned. By executing a step counter update microinstruction in a microprogram that implements an instruction to return to the original software program, the step counter 5 can be updated as follows. When the step counter update microinstruction is read from the control memory 41 to the microinstruction register 44, its contents are decoded by the decoder 45, and the decode signal d becomes "1". An AND signal of the decode signal d and the negation of the value held in the register 6 serves as a count-up signal for the step counter 5.

Since the register 6 has already been reset, it holds "0", and when the decode signal d becomes "1", the step counter 5 amplifies one count. Due to the above,
Each time the last step of the instruction program for realizing the second type instruction is executed, the step counter 5 counts up by one, so that the number of steps of the software instruction can be accurately measured.

In the above embodiment, the step counter 5 is counted up, but the present invention is not limited to this, and the step counter 5 may be set to a predetermined initial value and then counted down. [Effects of the Invention] As explained above, the present invention sets a register at the same time as the execution of an instruction program for realizing the second type of instruction starts, and resets the register at the time of execution of an instruction indicating the end of execution of the instruction program. By doing this, it is possible to suppress the count up of the step counter during the execution of the instruction program to implement the type 2 instruction, so it is possible to prevent the step counter from counting up during the execution of the instruction program to realize the type 2 instruction. It is also effective in accurately measuring the number of executed instruction steps in an information processing device that realizes a second type of instruction by executing an instruction program from a certain type 1 instruction, and is effective for software performance analysis and debugging. be.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an embodiment of an information processing device according to the present invention, FIG. 2 is an explanatory diagram for explaining type 1 instructions and type 2 instructions, and FIG. 3 is a diagram showing a conventional information processing device. This is a system diagram shown. 1... Main memory, 2... Instruction fetish circuit, 3...
Memory for instruction analysis, 4... Control storage circuit, 5... Step counter, 6... Register, 11... Software program storage section, 12... Instruction program group storage section, 21... Instruction Address register, 22...
Instruction buffer register, 23... Branch address generation circuit, 24... Sequential address generation circuit, 25... Instruction counter, 26... Instruction counter save register, 41
...control memory, 42...microinstruction sequencer,
43...Micro address register, 44...Micro instruction register, 45...Decoder, 221...
Operand part of the instruction, 222... Instruction code part of the instruction. Patent applicant: NEC Corporation

Claims (1)

[Scope of Claims] An information processing device controlled by a microprogram stored in a control memory, comprising: a first type of instruction realized by a microprogram on the control memory; and the first type of instruction. a main memory for storing a second type of instruction realized by an instruction program; a register that is set at the start of the instruction program for realizing the second type of instruction and reset at the end of the instruction program; An information processing apparatus comprising: an instruction counting means that adds or subtracts one by one each time a software instruction is executed one step only when the register is in a reset state.