JPH02236734A - Emulation system for microprocessor - Google Patents

Abstract

PURPOSE:To enable emulation to be performed even when architecture is remarkably different by switching the output of an instruction decode unit and that of an emulation memory appropriately, and inputting them to a second microprocessor. CONSTITUTION:The instruction decode unit 3 fetches and decodes the instruction of a first microprocessor, and outputs the instruction of a second microprocessor 1 required for the emulation of the above instruction. Also, the emulation memory 4 holds another instruction of the second microprocessor 1 required for the emulation of the instruction of the first microprocessor. When the emulation is performed by using the second microprocessor having the architecture different from that of the first microprocessor, the output of the instruction decode unit 3 and that of the emulation memory 4 are switched appropriately and inputted to the second microprocessor 1. Thereby, it is possible to easily perform the emulation even by the microprocessor having remarkably different architecture.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor emulation system.

[Conventional technology]

Conventionally, when a first microprocessor having a specific architecture is emulated using a second microprocessor having a different architecture, the P embedded in the second microprocessor is
L A (Programmable Logic Ar
ray) or R O M (Read Only M
This has been realized by changing the emulation circuit such as Emory to one suitable for emulation of the first microprocessor.

[Problem to be solved by the invention]

Although emulation is possible with the conventional method described above, there is a limit to the scale of the emulation circuit that can be built into the microprocessor, so the architecture of the first microphone processor that is the target of emulation is changed to the second microprocessor. If the architecture is significantly different from that of the previous one, the disadvantage is that the internal emulation circuit is insufficient and emulation becomes difficult.

The present invention solves these conventional drawbacks,
The purpose is to provide a microprocessor emulation method that eliminates limitations on the scale of emulation circuits and enables emulation even when the architectures are significantly different. [Means for Solving the Problems] In order to achieve the above object, the present invention provides a method of emulating a first microprocessor having a specific architecture using a second microprocessor having a different architecture. an instruction decode unit that fetches and decodes the instructions of the first microprocessor and outputs the instructions of the second microprocessor necessary to emulate the instructions; an emulation memory for storing other instructions of the second microprocessor necessary for emulation, and the output of the instruction decoding unit and the output of the emulation memory are appropriately switched and inputted to the second microprocessor. I try to do that.

[Effect]

In the microprocessor sensor emulation system of the present invention, the instruction decoding unit decodes and decodes the instructions of the first microprocessor and outputs the instructions of the second microprocessor necessary for emulating the instructions; , an emulation memory retains other instructions of the second microprocessor necessary to emulate the instructions of the first microprocessor, and emulates a first microprocessor having a particular architecture with a different architecture. When performing emulation using a second microprocessor having a second microprocessor, the output of the instruction decode unit and the output of the emulation memory are appropriately switched and input to the second microprocessor.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of a microprocessor emulation system according to the present invention. This embodiment uses a microprocessor to be emulated (
The microprocessor (second microprocessor) 1 has a different architecture from that of the first microprocessor (first microprocessor), a memory 2, an instruction decode unit 3, and an emulation memory 4.

The second microprocessor 1 is a RISC (Reduce I) processor that executes most instructions in one clock.
n-structure Set computer)
type of processor, which is connected to a data bus 11, an address bus 12, and has its own instruction bus 21. The instruction address bus 22 is drawn out to the outside. The memory 2 is a memory that stores a program and data of a first microprocessor to be emulated, and is connected to a data bus 11 and an address bus 12.

The instruction decoding unit 3 is a circuit that fetches and decodes the instructions of the first microprocessor stored in the memory 2, and outputs predetermined instructions of the second microprocessor l necessary for emulating the instructions. , a data bus l1, an address bus 12, an instruction bus 21 . It is connected to the signal line 31 and the signal line 32.

The emulation memory 4 is a memory that stores other instructions of the second microprocessor 1 necessary for emulating the instructions of the first microprocessor, and includes the instruction bus 21. Instruction address bus 22. It is connected to the signal line 32 and the signal line 31. Here, when the signal line 32 is set to a predetermined level, for example, a logical value "1" by the instruction decode unit 3, the emulation memory 4 transfers the instruction stored in the location specified by the address of the instruction address bus 22 to the instruction bus. Output to 21. Also, when one section of emulation is finished, the signal line 3
By setting the level of 1 to a predetermined level, such as a logical value of "1", the instruction decode unit 3 is notified of this fact. The outputs of the instruction decode unit 3 and the emulation memory 4 are both input to the second microprocessor l via the instruction bus 21, but while one outputs a valid signal, the other is in a high impedance state. As shown, both outputs are selectively supplied to the second microprocessor 1 without interfering with each other.

When emulating with the configuration shown in FIG. 1, the program and data of the first microprocessor to be emulated are stored in the memory 2. Further, some of the instructions of the second microprocessor 1 necessary for emulating each instruction are generated by the instruction decode unit 3 (in other words, the instruction decode unit 3 is created in advance in this way). Then, the remaining instructions necessary for emulation are stored in the emulation memory 4. When the emulation operation is started, the instruction decoding unit 3 retrieves and decodes the instructions of the first microprocessor from the memory 2, and sequentially decodes the instructions of the second microprocessor l necessary for emulating the instructions. is generated and supplied to the microprocessor l via the instruction bus 2I. At this time, in this embodiment, when the fetched instruction is a specific instruction, the instruction decode unit 3 generates and outputs all the plural instructions for emulating it, and for other instructions, only one instruction is generated. The instruction decode unit 3 generates only a predetermined instruction among the plurality of instructions necessary for emulating one instruction, and the remaining instructions are read from the emulation memory 4. In the latter case, the instruction decode unit 3 sets the level of the signal line 32 to the logical value "1" at an appropriate timing.

As a result, the instruction read from the location specified by the instruction address bus 22 in the emulation memory 4 is supplied to the second microprocessor 1 via the instruction bus 2l. The second microprocessor 1 has an instruction bus 21
It executes instructions supplied via the internal registers, and performs additions between internal registers and data bus
2, and as a result emulation of the instructions of the first microprocessor is achieved.

Next, specific examples of the instruction format of the first microprocessor to be emulated and the instruction format of the second microprocessor 1 that performs emulation will be explained.
The operation of this embodiment will be explained in more detail using one instruction of the first microprocessor as an example.

Figure 2 shows the instruction format of the first microprocessor.
In the figure, field f21 is a field for storing an operation code OP, and field f22 is a field for storing an operation code OP.
The field f23 indicates the register R1 which is the operand, the field f23 indicates the index register X2, and the field f24 indicates the pace register B2.
Field [25 is a field that stores displacement value D2. The value (X2) stored in the index register X2, the value (B2) stored in the pace register B2, and the displacement value D2 are added to obtain the memory address that becomes the second operand. Figure 3 (al. (bl, tc
) indicates the instruction format of the second microprocessor 1. In FIG. 3(a), field [31 is a field for storing the overlapping code OP, field [32 is a destination register RAt-, field f3
3 is a field indicating source register RB, and field f34 is a field indicating source register RC. In addition, in FIG. 3B, field f35 is a field for storing an operating code oP, and field f3 is a field for storing an operating code oP.
6 is a field that stores a branch destination address (BRANCH ADDRESS) when the instruction is a branch instruction. Furthermore, in the same figure (in Cl, field [3
7 is a field that stores the operation code OP;
Field f3B is a field that specifies destination register RA, and field ``39'' is a field that stores immediate data (IMMEDIATE DATA). The first microprocessor's load instruction (an instruction to transfer an operand in memory to a register, which is expressed in the instruction format shown in FIG. 2) is a field f2
3, f24, the contents of the memory address obtained by adding the contents of index register
), which is an instruction to transfer to
For example, six instructions of the second microprocessor 1 shown in FIG. 4 are used. Here, for commands ■～■, the first
The instructions 1 to 2 are generated by the instruction decode unit 3 shown in the figure, and are stored in the emulation memory I74. The contents of each command are as follows.・Instruction ■ FIG. 3 (This is a Cl type instruction, and is an instruction to transfer the displacement value D2 to the general-purpose register R36 in the second microprocessor 1.

・Instruction ■ Figure 3 (This is an alO type instruction, and an indirect pointer IPRC that specifies the source registers RC, RB and destination register RA in the second microprocessor 1)
, IPRB and IPRA, each field value X2,
This is an instruction to transfer B2 and Rl.

Instruction (2) This is an instruction of the type shown in FIG. 3 ('b), and is an instruction to branch to the instruction (2) stored in the emulation memory 4 to be executed subsequently.

・Instruction■ Figure 3 (alO type instruction, indirect pointer IPRC
, the contents of general-purpose registers X2 and B2 indicated by IPRB (
This is an instruction to add X2) and (B2) and theft to general-purpose register R34.

・Instruction■ This is also an instruction of the type shown in Figure 3 (In), and is an instruction to add the contents of general-purpose register R34 ((X2) + (B2)l and the contents D2 of general-purpose register R36 and set it to general-purpose register R35. . ・Instruction ■ Also shown in Figure 3 (This is an alO type instruction, and the address is the contents of general-purpose register R35 ( ( (X2) + (B2) +
D21 ) The contents of memory 2 indicated by indirect pointer I
This is an instruction to transfer to general-purpose register RA indicated by PRA. It should be noted that when this instruction (2) is read out, a logic value "1" is output from the emulation memory 4 to the signal line 31.

In operation, first, the instruction decode unit 3 fetches the load instruction of the first microprocessor from the memory 2, decodes it, generates an instruction, and outputs it to the instruction bus 21. When the second microprocessor l receives this instruction (2), it transfers the displacement value D2 in the instruction (2) to the internal register R36. At the next clock, the instruction decoding unit 3 generates the instruction (2) and outputs it to the instruction bus 2l, and the second microprocessor l responds to this by generating the instruction (2) in the internal source register RC. The values of each field of instruction (2) are transferred to indirect pointers IPRC, IPRB, and IPRA that specify RB and destination register RA.

At the next crosshair, the instruction decode unit 3 generates the instruction (2) shown in FIG. 4 and outputs it to the instruction bus 21.

The instruction ■ is a branch instruction, and upon receiving it, the second microprocessor 1 sets the branch destination address specified in the field of the instruction ■ in the program counter PC. The branch destination address is the address of the instruction (2) stored in the emulation memory 4 to be executed subsequently, and this address is output to the instruction address bus 22. Further, the instruction decode unit 3 sets the level of the signal line 32 to a logical value "1" in synchronization with the execution of the instruction (2), and outputs the output of the emulation memory 4 to the instruction bus 21. Therefore, at the next clock, emulation memory 4
4 is output to the instruction bus 21, and the second microprocessor 1 outputs the indirect pointers IPRC and IPR.
Contents of general-purpose registers RC and RB indicated by B (X2),
(B2) is added and transferred to general-purpose register R34. At this time, the program counter PC is updated and the instruction address bus 22 reads the instruction on the emulation memory 4.
Indicate the location of

Continuation 《Instruction ■ is output from the emulation memory 4 to the instruction bus 21 with the clock. By receiving this instruction ■, the second microprocessor l receives the general-purpose register R3.
Contents of 4 { (X2) + (B2)} and general-purpose register R
The contents D2 of 36 are added and sent to the general register R35. As a result, the memory address of the second operand in the load instruction (((X2)+
(B2)+D2) ) has been created. Note that the program counter PC is updated at this time. At the subsequent clock, the instruction (2) is read from the emulation memory 4 and supplied to the second microprocessor (1). In response, the second microprocessor 1 accesses the address of the memory 2 held by the general-purpose register R35, and transfers its contents to the general-purpose register RA indicated by the indirect pointer IPRA. Execution of this instruction ■ completes the emulation of the load instruction.

In synchronization with the emulation memory 4 outputting the instruction ■ to the instruction bus 21, the level of the signal line 3l changes to the logical value "1".
When the instruction decode unit 3 detects this, it decodes the first microprocessor instruction that has already been fetched from the memory 2 and is to be executed next, and transfers the created second microprocessor instruction to the instruction bus. 21 and starts emulating the next instruction. Note that the level of the signal line 31 is changed to the logical value "l" in synchronization with the output of the command
For example, a configuration in which an additional bit with a logical value of "1" provided at the same address as the instruction (■) is outputted to the signal line 31 can be adopted. In this example, the instruction that the instruction decode unit 3 outputs to the second microprocessor 1 is based on the register specification field, displacement value, etc. included in the instruction of the first microprocessor. These are an instruction to set immediate data in a register in the second microprocessor 1 and an instruction to branch to the emulation memory 4. Other instructions are output from the emulation memory 4 to the second microprocessor 1. Furthermore, as described above, it is also possible for the instruction decoding unit 3 to output all instructions of the second microprocessor 1 for emulation of a specific instruction of the first microprocessor. In order to fully utilize the performance of the second microprocessor 1,
It is necessary to supply instructions quickly.

Achieving this with emulation memory 4 would require a high-speed, large-capacity memory, leading to an increase in price and mounting space, which is not a good idea. In contrast, the instruction decode unit 3 can supply instructions relatively inexpensively and at high speed. Therefore, for emulation of a specific instruction of the first microprocessor that needs to be executed at high speed, the instruction decoding unit 3 supplies all the instructions of the second microprocessor l, and for emulation of a specific instruction of the first microprocessor that needs to be executed at high speed, Regarding the emulation of the instructions of the microprocessor 1, if the instructions are also supplied from the emulation memory 4, relatively high-speed emulation can be achieved at an appropriate cost.

〔Effect of the invention〕

As explained above, the microprocessor emulation method of the present invention transmits and decodes the instructions of the first microprocessor to an external device of the second microprocessor used for emulation of the first microprocessor. an instruction decode unit that outputs the instructions of the second microprocessor necessary to emulate the instructions of the second microprocessor, and an emulator that stores other instructions of the second microprocessor that are necessary to emulate the instructions of the first microprocessor. The size of the instruction decode unit and emulation memory can be arbitrarily set independently from the second microprocessor, making it possible to easily emulate microprocessors with significantly different architectures. Become. In addition, the instructions for the second microprocessor necessary to emulate the instructions for the first microprocessor are supplied not only from the emulation memory but also from an instruction decode unit that can supply instructions at high speed. For emulation of specific instructions of the first microprocessor 1 that should be executed at high speed, the instruction decode unit supplies all instructions of the second microprocessor 1. As for the emulation of the instructions of the first microprocessor that do not need to be executed at a very high speed, by supplying the instructions from the emulator memory as well, relatively high-speed emulation can be achieved at a reasonable cost. be. As a result, according to the present invention, it is possible to quickly emulate a microprocessor with a dedicated architecture used for each application with a general-purpose high-speed microprocessor, thereby improving the performance of devices and systems. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of the present invention, FIG. 2 is a diagram showing the instruction format of the first microprocessor, FIG. 3 is a diagram showing the instruction format of the second microprocessor, and FIG. FIG. 4 is a diagram showing an example of instructions supplied to the second microprocessor when emulating and executing a load instruction of the first microprocessor. In the figure, 1... second microprocessor 2... memory 3... instruction decode unit 4... emulation memory 11... data path 12... address bus 2l... instruction bus 22... ...Command address bus 31, 32...Signal line Patent applicant: 1 person other than NEC Corporation

Claims (1)

[Scope of Claims] A method for emulating a first microprocessor having a specific architecture using a second microprocessor having a different architecture, comprising: fetching and decoding instructions of the first microprocessor; and the second instruction necessary to emulate the instruction.
an instruction decode unit that outputs instructions of the second microprocessor; and an emulation memory that stores other instructions of the second microprocessor necessary for emulating the instructions of the first microprocessor; A microprocessor emulation system characterized in that the output of the unit and the output of the emulation memory are switched as appropriate and inputted to the second microprocessor.