JPH02236737A - Data code error detection circuit - Google Patents

Abstract

PURPOSE:To detect the operating state of the input side circuit of a circuit to be monitored by branching an input data signal into two, setting the data signal on one side as a monitor signal for a circuit equivalent to the circuit to be monitored by applying a certain pattern of scrambling, and comparing it with the output of the circuit to be monitored by applying descrambling afterwards. CONSTITUTION:One of the input data signal branched into two is scrambled by a scrambling circuit 2 according to a certain pattern. The monitor signal 3 outputted from the scrambling circuit 2 is inputted to the circuit 11 equivalent to the circuit 4 to be monitored, and is descrambled at a descrambling circuit 7, then, is returned to an original monitor signal. The exclusive OR of a descrambled data signal 8 and the data signal 5 passing the circuit 4 to be monitored is taken, and the bit comparison of the data signal is performed. Therefore, the logic of the data error output of an exclusive OR circuit 9 goes to 0 when the input side circuit of the circuit 4 to be monitored is set at the operating state, and the logic of the exclusive OR circuit 9 goes to 1 when it is not set at the operating state. Thereby, confirmation of the operating state of the circuit to be monitored is accurately performed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data code error detection circuit for monitoring circuit operations within a device involved in digital data transmission.

(Prior art) Conventionally, rounding data code error detection circuits that monitor circuit operations have adopted methods that use parity checks, such as those that use odd parity and those that use even parity. .

(Problems to be Solved by the Invention) In the conventional circuit operation monitoring data code error detection circuit, when the input side circuit of the monitored circuit stops operating, it is not possible to detect it as a data code error. The ninth drawback is that it is not possible to accurately confirm the operating status of the monitored circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data code error detection circuit capable of detecting the operating state of an input side circuit of a monitored circuit.

(Measures to Solve the Problems) In order to achieve the above object, the data code error detection circuit according to the present invention includes a monitored circuit that inputs an input data signal and outputs the data signal, and a circuit that receives the input data signal and outputs the data signal. a scrambling circuit that branches a signal and scrambles the branched data signal as a monitoring signal according to a certain pattern; a circuit equivalent to the monitored circuit that receives the output of the scrambling circuit as an input; It consists of a descrambling circuit that descrambles the circuit output, and an exclusive OR circuit that takes the exclusive OR of the output of the descramble circuit and the output of the monitored circuit and performs a bit comparison of data.

(Example) Hereinafter, with reference to the drawings, this E! A will be explained in more detail. FIG. 1 is a block diagram showing an embodiment of a data code error detection circuit according to the present invention.

Input data signal 1 is branched into two.

The 910,000 input data signals 1 divided into two are scrambled by a scramble circuit 2 according to a certain pattern.

A monitor signal 3 output from the scramble circuit 2 is input to a circuit 11 equivalent to the monitored circuit 4, and its output 6 is descrambled by a descramble circuit 7 and returned to the original monitor signal.

This descrambled next data signal 8 is sent to the monitored circuit 4.
The exclusive logic MJ is taken from the data signal 5 that has passed through '5c, and the bits of the data signal are compared.

Therefore, if the input side circuit of the monitored circuit 4 is in the operating state, the logic of the data error output of the exclusive OR circuit 9 is O.
Therefore, if it is not in the operating state, the logic of the exclusive OR circuit 9 becomes 1.

(Effects of the Invention) As explained above, the present invention splits the input data {i} into two, scrambles the 10,000 data signals in a certain pattern as a monitor signal, and inputs them to a circuit equivalent to the monitored circuit. After that, by descrambling and comparing with the output of the monitored circuit, it is possible to determine whether the input side circuit of the monitored circuit is not operating.
This method is effective in that it is possible to accurately check the operation of the monitored circuit in order to detect an error as a code error in a repeating pattern in the desk 2 sample circuit even if it cannot be detected with odd parity or even parity.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a circuit operation monitoring circuit according to the present invention. 1... Input data signal 2... Scramble circuit 3... Scrambled data signal 4... Monitored circuit 5... Data signal 6... Scrambled data signal 7... Descrambled Circuit 8...Descrambled friend data signal 9...EX
-OR gate 10... Data error output patent tk3 applicant NEC Co., Ltd. Same as above Miyagi NEC Co., Ltd.

Claims (1)

[Claims] a monitored circuit that inputs an input data signal and outputs a data signal; a scramble circuit that branches the input data signal and scrambles the branched data signal as a monitor signal according to a certain pattern; and a scramble circuit that outputs the output of the scramble circuit. a circuit equivalent to the monitored circuit as an input;
The device comprises a descrambling circuit that descrambles the equivalent circuit output, and an exclusive OR circuit that performs an exclusive OR of the output of the descramble circuit and the output of the monitored circuit, and performs a bit comparison of data. A data code error detection circuit characterized by: