JPH02236748A - Store buffer - Google Patents

Abstract

PURPOSE:To improve the throughput of an information processor as a whole by issuing a request to affect a store request in which the fact that no store address in a store buffer is included in a block address is confirmed on a cache memory while performing block loading when mis-caching occurs. CONSTITUTION:When a read request to the cache memory at a state where the store request is held at the entry of the store buffer 33 is issued, a comparison means 16 compares an address relating to the store request held at the entry with the address relating to the read request in block unit. When the mis-caching occurs in the read request, a set means sets a storable display means corresponding to the entry in which the output of the comparison means displays anticoincidence. When data loading from a main storage to the cache memory is performed, a request generating means 32 generates the request to affect the store request on the cache memory. Thereby, it is possible to heighten the performance of the information processor by preventing the residence of the store request in the store buffer for a long time occurring.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a cache used in an information processing device.
Concerning store buffers in memory devices. [Prior Art] Many of today's information processing devices employ cache memory devices to improve memory access time. Additionally, many of these that employ a pipeline processing method have a storage means called a store buffer that temporarily holds addresses and data related to store requests, independent of the cache memory. The reason why a store buffer is necessary is that store requests are given a lower priority than memory read requests and must be waited for, and the second reason is that store requests are given lower priority than memory read requests and must be waited for. This is to adjust the time lag between the generation of data and the creation of store data. Store requests stored in the store buffer are reflected in the cache memory between memory read requests. If a subsequent memory read request requires store request data in the store buffer that has not yet been reflected in the cache memory, the old data in the cache memory is used as data for that memory read request. Giving back should be avoided. Therefore, when reading the cache memory in response to a memory read request, the memory address is compared with the address of the store request in the store buffer, and if the read address and store address match, When detected, the read operation is temporarily stopped and the store request in the store buffer is reflected in the cache memory. When processing of a request that can be reflected in the cache memory in the store buffer (a store request for which the address and data are complete) is completed, the processing of the previous read request is retried, and any discrepancies in instruction execution are resolved. control so that this does not occur. In this way, the store request in the store buffer is reflected in the cache memory when the cache memory is in the following state. (1) There is no read request. (2) When the read address and the store address in the store buffer match.

[Problem that the invention seeks to solve]

However, in today's information processing devices, there is always an instruction read for each instruction, and at least 60% of the operands are read, so read requests almost never disappear, and the store in the store buffer Currently, the request is reflected in the cache memory based on a comparison between the read address and the store address. However, the capacity of the store buffer is usually about 4 to 16 words, and if the read address and store address do not match for a long period of time, if the store request is stored to the full capacity, the subsequent store command cannot be executed. Then, there will be no more read requests, and it will naturally become possible for store requests to be reflected in the cache memory. This not only causes an interruption in instruction execution, but also
The supply of instructions will also be interrupted. Therefore, it is desirable to be able to process store requests before the store buffer is full. By the way, if a copy of the address of a memory read request does not exist in the cache memory (cache miss), it is necessary to stop subsequent requests and load data from the main memory to the cache memory (block load). be. At this time, since there is no subsequent read request, the condition (1) above is satisfied, and it should be possible to reflect the store request in the cache memory. When a store request is made,
After the store request is reflected in the cache memory, a block load is written to the cache memory, which may cause a conflict. For this reason, conventionally there is a restriction that prohibits store requests from being reflected in cache memory during block loading. Therefore, in low-locality applications where store requests are delayed further and cache misses occur frequently, the above-mentioned instruction execution and retrieval interruptions are likely to occur, leading to performance degradation. This is the cause. The present invention has been made in view of the above circumstances, and its purpose is to enable store requests to be reflected in the cache memory during block loading.
The purpose is to improve the performance of information processing equipment by preventing it from staying in the buffer for as long as possible. [Means for Solving the Problems] In order to achieve the above object, the present invention provides a store buffer including a plurality of entries in which a store request is not immediately reflected in the cache memory but is temporarily buffered.
The address associated with each store request held in the entry of the store buffer and the address associated with the read request to the cache memory are divided into blocks, which are management units of a predetermined number of words, in the cache memory. a comparison means for comparing; a setting means for setting a storable display means corresponding to an entry for which an output of the comparison means indicates a mismatch when the read request causes a cache miss; reset means for resetting all of the storable indication means when loading data from the main memory to the cache memory; and request generation means for generating a request to reflect in the cache memory a store request for an entry to which the means is set. (Operation) In the store buffer of the present invention, when there is a read request to the cache memory while a store request is held in an entry in the store buffer, the comparison means reads the store request held in the entry. and the address related to the read request in block units, and when the read request causes a cache miss, the setting means can store the entry corresponding to the entry for which the output of the comparing means indicates a mismatch. When the display means is set and data is loaded from the main memory to the cache memory triggered by the cache miss, the request generation means caches the store request for the entry for which the store possible display means is set. A request to reflect the data to the memory is generated.Furthermore, when the data loading is completed, the reset means resets all of the storable display means and returns the storable display means to the initial state.[Example] Next , an embodiment of the present invention will be described in detail with reference to the drawings. Referring to FIG. 1, the store buffer 33 of one embodiment of the present invention is a cache store address buffer (hereinafter referred to as CSAB). 1, a cache store data buffer (hereinafter referred to as csDB) 2, an address set pointer (hereinafter referred to as AS) 3, an address read pointer (hereinafter referred to as AR) 4, and a data
A set pointer (hereinafter referred to as DS) 5, a data read pointer (hereinafter referred to as DR) 6, a non-hazardous flag group (hereinafter referred to as NHF) 7, and a request generation circuit (hereinafter referred to as RG).
32). Each has the following configuration and functions. - This is a pointer that points to the entry in CSABl where the address of the AS3 store request should be stored next. - AR4 This is a pointer pointing to the next entry of the CSABl entry for which the store request has been reflected up to now.・CSAB 1 Multiple entries (for example, 4 entries in this embodiment) that hold addresses of store requests sent from the instruction processing unit
The address of the store request is buffered by holding the address in these multiple entries.
Also, the address and cache information held in each entry are
A comparison means that compares the address of a read request to memory in all bits and block units, and a cache miss signal C indicates that the read request has caused a cache miss.
It has a setting means for setting a logical value "1" to a flag of NHF7 corresponding to an entry indicating that the output of the comparison means is undefeated when notified by ACMrS. Referring to FIG. 2, CSAB 1 includes a decoder 203 that decodes the output of AS3, a decoder 204 that decodes the output of AR4, and a master latch group 205.4 latches that temporarily holds the address of a store request from the instruction processing unit. consisting of s. Comparators 207 to 210 and a decoder 204 that compare the output of each latch of the slave latch group 206 and the slave latch group 206 with the read request address
An address selector 211 selects one output from all the latches of the slave branch group 206 according to the decoding result and outputs the address associated with the store request to the address selector 9 and the main memory, which will be described later. Miss signal CACMIS and each comparator 207 to 21
It includes gates 212 to 215 which take the output of 0 as input and generate a signal to set the corresponding flag in the NHFT. Also, referring to FIG. 3, each comparator 207 to
210 is a comparator 301 that compares the block address included in the output of the corresponding latch of the slave branch group 206 and the block address among the read request addresses;
It consists of a comparator 302 that compares addresses within each block included in each block, and an AND gate 303 that takes the AND of the outputs of the comparators 301 and 302. When the block addresses of the latched store request address and read request address are equal, the output of the comparator 301 becomes a logical value "1", which is applied to the gates 212 to 21 in FIG.
Added to 5. Further, when both addresses are completely equal, the output of the AND gate 303 becomes a logical value "1".

The output of this AND gate 303 is used for "store check". Returning to FIG. 1 again, the remaining elements in the store buffer 33 will be explained.

・Contains flags that correspond to entries in NHF7 CSAB 1 on a one-to-one basis. Each flag contains a second flag at the timing of a cache miss when the address held in the corresponding entry in CSABI and the read request address are not in the same block.
A logic value "1" is set by the outputs of the gates 212 to 215 in the figure.

Further, all flags of the NHF7 are reset at the last reply (LRPLY) of a block load executed in response to a cache miss. Note that, referring to FIG. 2, the NHF 7 has a flag group 7' corresponding to each entry, and a selector 222 that selects one from the output of all flags of the flag group 7' according to the output of the decoder 204 and outputs it as NHFout. It is made up of.・CSDB2 Has multiple entries (four in this embodiment) that hold the data of store requests sent from the instruction processing unit, and buffers the data of store requests by holding data in these multiple entries. conduct. - DS5 This is a pointer to the entry in CSDB2 where the store request data should be stored next. - DR6 This is a pointer pointing to the next entry of the CSDB2 entry for which the store request has been reflected up to now.

- RG32 Inputs the output of DS5, the output of AR4, the block loading signal OBL indicating whether or not a block is being loaded, and the output NHFout of NHF7, and generates store requests ST, REQ and store end signals ST, END. In particular, in this embodiment, data is transferred from main memory to cache memory.
During loading, if there is a flag of NHF7 displaying the logical value "1", a store request ST. REQ is issued. FIG. 4 shows an example of the configuration of this RG 32, which issues a normal store request and a store request during block loading.

In FIG. 4, a comparator 40l. which compares the output value of AR4 and the output value of DS5. Block loading signal OBL
is set as an inhibit input, and when the comparator 401 detects AR<DS during non-block loading, a store request ST. game that generates REQ}402, comparator 40
1 detects AR<DS, the store requests ST, REQ are executed while the output NHFout of NHF7 in FIG. 1 is "1".
A gate 403 generates a signal through a gate 404. Note that when the comparator 401 detects AR-DS,
Store end signals ST and END are generated. Referring again to FIG. 1, the parts shown in FIG. 1 other than the store buffer 33 are other components of the cache memory device. That is, other components include a status selector (hereinafter referred to as SAX) 8, an address selector (hereinafter referred to as AAX) 9. Data selector (hereinafter referred to as DAX)
(referred to as DCX)10,30. Status register (hereinafter referred to as SAR, SBR, SCR) 11.1B, 26.
Address register (hereinafter referred to as AAR, ABR, ACR) 12.19.27. Data register (hereinafter referred to as DAR)
, DBR, DCR) 13, 21.2B, Prior decoder (hereinafter referred to as PRIOR, DEC) 14.
Address array (hereinafter referred to as AA) 15 consisting of address section AAD and valid bit section V, comparator 16
, AND gates 17, 23, 24, hit register (hereinafter referred to as AHR) 20, status decoder (
(hereinafter referred to as SDEC)22. Data array (hereinafter referred to as DA)
) 25 and decoder 29.31 (hereinafter referred to as RDEC) are included in the cache memory device.
Each has the following configuration and functions. - AA update request from SAX8 RDEC3 1, store request ST. from store buffer 33. REQ, store end signal S
T. END. Each status related to a read request from the instruction processing section and a block load request from the main memory is input, and one of them is selected and output according to selection signals SELO to SEL3 output from PRIOR and DEC14.

- AA update address from AAX 9 ACR27. Store request address from store buffer 33. The read request address from the instruction processing section and the block load address from the main memory are input, and one of them is selected and output according to selection signals SELO to SEL3.・DAX 1 0 Store data from the store buffer 33 and load data from the main storage device are manually input, and the selection signal SELI
, select one of them according to SEL3 and output it. - Register that holds the output of SARII SAX8 - Register that holds the output of AAR 1 2 AAX9 - Register that holds the output of DAR 1 3 DAX1 0 - PRIOR,
DECl4 STBHIT signal, RD. REQ signal, MM. REQ
Signal, ST. REQ signal, OBL signal. UPD. REQ
signal, RSM, REQ signal as input, SAX8, AA
Output selection signals SELO to SEL3 to X9 and DAXIO. Figure 5 shows PRIOR. An example of the configuration of DEC14 is shown below. In addition, in FIG. 5, RSM. The REQ signal is a request to restart the request that was kept waiting in the SCR 26 and ACR 27 after the store request in the store buffer is purged due to a store buffer hit.
Generated by EC3 1. Also, MM. The REQ signal sends data read from the main memory to the DA25 when loading a block.
This is a request to write to a file, and is added from the main memory access control unit (not shown).・AA15 Consists of an address part AAD and a valid bit part ■.
The lower part of the address held in R12 (intra-block address) is used as the address input, the higher part (block address) is used as the data input of the address section AAD, and the SARI
The AA update request signal UPDATE at the output of I is used as the data input of the valid bit section V and the write enable WE.・The upper address (block address) held in the comparator l6 AAR 1 2 and the output Dou of the address section AAD of AA15
Detects a match with t (copy of block address).・AND gate l7 Performs the AND of the output of the comparator l6 and the output of the valid bit section V of AA15.・SBR1B Register that holds the output of SARII ・ABR19 Register that holds the output of AAR 1 2 ・AHR20 Register that holds the output of AND gate 17 ・DBR2
1 Register/SDEC2 that holds the output of DAR 1 3
2 SBR l B output and AHR20 output (CAC
The Load signal at the output of the decoder and gate 23 SBR 1 8 which inputs HIT) and AHR2
A logical product is performed with the output of 0 to generate a write enable signal for the DA25.

・Read signal at the output of AND gate 24 SBR1 8 and AHR20
, and generates one selection signal for DCX30.・DA25 DBR2 This is a group of registers that uses the output of 1 as a data input, the lower address (intra-block address) of ABRI9 as an address input, and the output of the AND gate 23 as a write enable. In addition, this DA25 and AA15
This constitutes the main part of the cache memory, and in the case of this embodiment, the method is a direct mapping method.

・SCR26 A register that holds the output of SDEC22. Its output is
It is sent to the instruction processing unit, main memory, or decoder 29.31.・ACR27 Holds the output of ABR19 and stores it in the main memory or AAX
The register DCX30 outputs to 9. The output of DA25 and the output of DBR21 are input, and one input is selected and output according to the First Reply signal at the output of AND gate 24 and the output of SBR18.・DCR28 Register decoder 29 that holds the output of DCX30 and outputs it to the instruction processing unit Decodes the output of SCR26 and outputs the OBL signal and STB
Generate HIT signal and LRPLY signal.・Decoder 3
1 Decodes the output of SCR26 and sends the AA update request to SA.
Output to X8. Next, the operation of this embodiment will be explained separately for each case. r Read operation 1 For a read request from the instruction processing unit, the status, which is a memory read request, is sent to SARII via SAX8.
sent to. At the same time, the requested address is stored in AAR12 via AAX9. In the next cycle (referred to as A cycle), AA15 is read by the lower address (intra-block address) of AAR12, and the output of the address section AAD is compared with the upper address (block address) of AAR12 in comparison 316. be exposed.

The output of the comparator 16 is the address part AAD in AAlS.
At the same time, the AND gate 17 performs a logical product with the valid bit of the valid bit section V read out by the lower address of the AAR 12, and the output is stored in the AHR 20. The operation after the next cycle (called B cycle) is AH
Depending on the output of R20, it can be divided into the following two types. i) AHR - When “1” (cache hit CA
CHIT): Lower address of the read request address moved from AAR12 to ABR19 in A cycle (intra-block address)
DA2 5 is addressed by, AHR20
The AND gate 24 takes the logical product (“1”) of the output of the SBR18 and the Read signal at the output of the SBR18, and the DC
The DA25 side of X30 is selected, and the output of DA25 is D
Stored in CR2B. In the same B cycle, SBR18
The output of the AHR 20 is converted by the SDEC 22 to indicate a cache hit and can be rewritten, and the S
It can be stored in CR26. In the next cycle (referred to as C cycle), a reply signal LRFLY is returned from the decoder 29 to the instruction processing section based on the output of the SCR 26, and the output of the DCR 2B is sent to the instruction processing section as read data. ii) When AHR is “0” (cache miss CAC
MIS): With the output of AHR2Q and the output of SBR lB,
DEC22 determines that it is a cache miss.
The output data of A25 is not stored in the DCR28 because the output of the AND gate 24 is a logical value "O", ABR1
The address held in 9 is transferred to ACR 27. In the next C cycle, a block load request is made to the main memory by the output of the SCR 26 with the address stored in the ACR 27. The request and address that caused the cache miss will be sent to SCR26 and ACR from now on.
27 and is held until the end of the pack load,
Subsequent requests stored in AAR12 and ABR19 are canceled, and after block loading is completed, the instruction processing unit resends them to the cache memory device. A decoder 29 generates a block loading signal OBL from the output of the SCR 26. At the same time as the block load request to the main storage device is sent, a new AA update request is generated by the RDEC 3 1 based on the status of the read request that caused the cache miss in the SCR 26, and this AA update request is sent to the SAX8
It is stored in SARII through. At the same time, ACR27
The address related to the read request held in AAX
9 and stored in rAAR12. When the A8 update request is stored in SARII, the AA update request signal UP
DATE causes the AAI5 write enable signal WE to
The input signal for the valid bit part V of AA15 is created.
As a result, the block address, which is the upper address of AAR12, and the valid bit indicating validity are written to the address indicated in the lower order of AAR12 in AAl5. With this operation, the operation for the AA update request ends. Now, the block load request sent to main storage is
In main memory, requests are broken down into requests for the number of words that make up a block of cache memory. For example, in this embodiment, if one block is composed of 8 words, a total of 8 words
block load requests from main memory to the cache.
Returns to memory device. This returned block load request is stored in SAR1l via SAX8. At the same time, the address to be loaded is also changed from the main memory to AAX.
9 and stored in AARl2. Furthermore, the data to be loaded is stored in DAR 1 3 via DAX 1 0. The A cycle in the block load indexes the AA15 using the intra-block address stored in the AAR12. Due to the previous AA update operation, the corresponding block address exists, so as a result, AHR20 has a logical value "
1" is stored. At the same time, the status moves from SARII to SBR1B, and the address moves from AAR12 to ABR.
19, and the data is from DAR1 3 to DBR2 1
Move to. In the B cycle, DA25 is addressed with the lower address (intra-block address) of ABR19, and SBR1
The output of the AND gate 23, which takes the logical product of the Load signal obtained from the output of B and the output of the AHR 20, has a logic value of "1".
'', the data held in DBR21 is written to DA25. At the time of the first block load request, this is recognized by the output of SBRI8, and the First Reply is sent.
The output of DBR21 is selected by the signal DCX301" and stored in DCR28. At the same time, the output of SBR1B is input to SCR26, and a reply is returned to the instruction processing section in the next C cycle. At this time as well, the decoder 29
The OBL signal has a logical value of "l" indicating that the block is being loaded. When the last block load request is returned from the main memory, the output of SBR1B is converted into a restart request by the SDEC 22 in the B cycle, and the awaited read request that caused the cache miss is restarted. rStore Operation 1 The address associated with the store request from the instruction processing unit is input to CSAB 1 of the store buffer 33, and is stored in the entry indicated by AS3 at that point. After that, AS3
is incremented to indicate the next entry. When the instruction processing unit finishes executing the instruction, the data related to the store request is input to CSDB2 of the store buffer 33, and is stored in the entry indicated by DS5 at that point.DS5 then points to the next entry. Increased. A store request is reflected in the cache memory as follows when a block is not being loaded. In the comparator 401 shown in FIG. 4 of RG32, the value of AR4 points to the entry next to the entry in CSAB1 for which the store request has been reflected until now, and the value of AR4 points to the entry next to the entry for which the current address and data are complete. If AR<DS holds true, the store requests ST and REQ generated by the gate 402 are sent to the cache memory, that is, to the SAX8. If the store request is cached
If it is accepted on the memory side, AR4 and DR6 are increased to point to the next entry. The above operation is shown in Figure 6. In addition, ite, D, A,
OFI, OF2, E, and W are the stages of the instruction execution byline, D is the instruction decoding stage, A is the operand address calculation stage, and OFI is the first stage of reading the operand, and AA15 is This is the indexing stage. OF2 is the second stage for reading out the operand and is the stage for reading out DA25. E is DA2
5 is a stage in which operations are performed on the operands read out, and W is a stage in which the operation results are written to the store buffer.
The subsequent "data registration" is a stage in which the calculation results read from the store buffer are sent to the AA15.
, OF2, and H correspond to cycles A, B, and C of the read operation described above, respectively. Next, the operation when the store request address in the store buffer 33 and the memory read request address match will be described. A match check between the store address and read address is called a "store check." Store check is executed at ABR19 stage when read request is at ABR19 stage.
and the contents of each entry in CSAB 1 are compared by comparators 207 to 210 in FIG. At this time, all address bits are checked. That is, the output of AND gate 303 in FIG. 3 is used. If a match is detected, the read request corresponding to the address in ABR19 (status is in SBR 18) will be placed in a state of Store Buffer Hit (STBHIT), and the status of SBR1B will be changed to a status of STBHIT by SDEC22. The status and address related to the read request are held in the SCR 26 and ACR 27 stages until the store request from the store buffer 33 is converted and reflected in the cache memory. The subsequent requests in AAR l 2 and ABR l 9 are canceled, and after the request in ACR 27 is restarted, it is sent again from the instruction processing unit. The state STBH IT is recognized by the decoder 29 from the output of the SCR 26. Now, when the read request is suppressed by STBHIT, the store request from the store buffer 33 is accepted by the cache memory. That is, the status related to the store request is stored in SARII through SAX8,
The address is stored in AAR12 through AAX9. Then, from now on, the cache due to this store request will be
Writing to memory is performed in the same way as described above. RG32 in the store buffer 33 is
The store request continues to be issued until the value becomes equal to ST. With this signal, the read request that has remained in the C stage is restarted, and subsequent requests are accepted in sequence. Next, we will discuss the store check at the time of a cache miss. If a cache miss and a store buffer hit occur at the same time, the store buffer
Prioritize hits. Then, after the store request is reflected, it is restarted with CACMIS to ensure that there are no inconsistencies. In order to make it possible to reflect store requests during block loading, which is a feature of the present invention, when CACMIS
Comparators 207 to 210 of CSAB 1 compare the read address that caused the IS with the store address in the store buffer 33. This is the comparator 207
In the comparator 301 of FIG. 3, which shows an example of the configuration of .about.210, only each block address is checked. That is, it is checked whether the store request address in the store buffer 33 at that time exists in the block that includes the address that caused the CACMIS. If the store address of a certain entry in the store buffer 33 does not fail, the gates 212 to
The output of 215 determines the NHF corresponding to that entry.
The logical value “B” is set in the flag of 7. If there is one defeat, the logical value “0” remains. This flag is
This is done for all entries between 3 and AR4. When a block load starts due to a cache miss, read requests are suppressed, so the cache memory side can accept store requests. At this time, the store request for each entry in the store buffer 33 is made when the flag of NHF7 for that entry is set to a logical value of "1".
”, and if an entry is found in which the flag of NHF7, which is issued from gate 403 of RG32 in FIG.
Store requests from 03 will be suppressed from then on. Then, the store request issued in this manner is processed in the same manner as described above, and all flags of NHF7 are reset to the logical value "0" by the LRPLY signal at the last block load request. [Effects of the Invention] As explained above, the present invention has the following advantages:
The store address in the store buffer is cached.
By checking whether or not the store request is included in the block address to be block loaded due to a mistake, and requesting that the store request is not included in the block address, it is requested to be reflected in the cache memory during the block load. Since store requests can be reflected from the store buffer to cache memory during block loading, store requests can be processed quickly, reducing interruptions in instruction execution and improving the overall performance of information processing equipment. Processing capacity can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a main part of a cache memory device including a store buffer according to an embodiment of the present invention, and FIG. 2 shows a cache store address buffer (CSAB) 1 and a non-hazardous flag group (NHF) 7. 3 is a block diagram showing an example of the structure of the comparators 207 to 210, FIG. 4 is a block diagram showing an example of the structure of the request generation circuit (RG) 32, and FIG. Decoder (PRIOR.DEC)
14 is a block diagram showing an example of the configuration, and FIG. 6 is a time chart showing the operation of a store instruction. In the figure, 1... Cache store address buffer (C
SAB) 2...Cache store data buffer (CS
DB) 3... Address set pointer (AS) 4...
Address read pointer (AR) 5...Data
Set pointer (DS) 6...Data read pointer (DR) 7...Non-hazardous flag (NHF) 8...Status selector (SAX) 9...Address selector (AAX) 10... ...Data selector (DAX) 11...Status register (SAR)
12... Address register (AAR) 13... Data register (DAR) l4... Brior decoder (PR[OR.DEC) 15... Address array (AA) 16... Comparator 17...AND gate 18...Status register (SBR) l9...
Address register (ABR) 20...Hit register (AHR) 21...Data register (DBR)
22...Status decoder (SDEC) 23.2
4...AND gate 25...Data array (DA) 26...Status register (SCR) 27...
Address register (ACR) 28...Data register (DCR) 29...Decoder 30...Address selector (DCX) 31...Decoder (RDEC) 32...Request generation circuit (RG) 33 ...Store buffers 203, 204...Decoder 205...Mask latch group 206...Slave latch group 207-210...Comparator 211...Address selectors 212-215... Gate 222... Selector 301, 302... Comparator 303... AND gate 401... Comparator 402-404... Gate 501-505... Gate

Claims (1)

[Scope of Claims] In a store buffer including a plurality of entries in which store requests are temporarily buffered without being immediately reflected in the cache memory, an address related to each store request held in an entry of the store buffer and an address of the cache memory are stored. Comparing means for comparing an address related to a read request to memory in units of blocks, which are management units of a predetermined number of words in the cache memory; and when the read request causes a cache miss, the comparing means a setting means for setting a storeable display means corresponding to an entry whose output indicates a mismatch; and a set means for setting a storeable display means at the end of data loading from the main memory to the cache memory triggered by the cache miss; and generating a request to reflect a store request for an entry set in the store possible display means to the cache memory during data loading from the main memory to the cache memory. A store buffer comprising a request generating means.