JPH02236785A - Picture signal processor - Google Patents

Abstract

PURPOSE:To make respective blocks common, to integrate the blocks and to make a picture signal processor compact and light by executing signal processing concerning one picture element by feedback loop processing by using a look-up table, computing element and bus for feedback. CONSTITUTION:A look-up table 20 is composed of a single large capacity memory, which can execute LUT processing by Nmax time, and a part to execute respective processing such as band compression, etc., is integrated. A computing element 21 can execute calculation by N-1max times and a part to execute processing such as primary color conversion and secondary color conversion, etc., is made common and integrated. For the look-up table 20 and computing element 21, a feedback loop is formed by a feedback bus FB.BUS as a whole. In such a way, the picture signal processing is executed by the plural times of the loop processing in the memory and arithmetic means through a feedback means. Thus, the respective blocks can be made common and integrated and the picture signal processor can be realized to be suitable for making the processor compact and light.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image signal processing device, and more particularly to an image signal processing device capable of high-speed processing.

(Background of the Invention) In conventional image signal processing devices, a method of directly sequentially processing input signals (real-time processing) has been common. And these were usually not given any feedback.

FIG. 4 is a block diagram showing a conventional example of such a structure. In this figure, 1 is the first block that performs the first process, 2 is the second block that performs the second process, 3 is the i-th block that performs the i-th process, and 4 is the n-th process. This is the nth block that performs the following.

In addition to this, a device with a complicated circuit configuration, in which individual blocks are intertwined with each other and each function within the system is configured with separate hardware, will be shown below.

FIG. 5 is a block diagram showing a general conventional example of such a structure. In this figure, 11 is a band compression circuit that performs band compression on image input, and 12 is a conversion circuit for converting the color of the image input signal (first-order color correction calculation processing equivalent to photographic masking).
13 is a black generation circuit that extracts gray components from each color component to generate black; 14 is a secondary color conversion circuit that adjusts the amount of desired hue; 15 is an undercolor removal circuit ( 16 is a USM circuit for improving sharpness, and 17 is a gradation circuit for adjusting tone changes from highlights to shadows.

(Problems to be Solved by the Invention) As described above, since the signal blocks (circuit blocks that perform respective signal processing) are provided individually, there is a drawback that the number of parts is large and the device becomes large.

Furthermore, as the number of parts increases, it becomes difficult to improve reliability in assembly and adjustment.

FIG. 6 is an explanatory diagram showing the configuration of FIG. 5 shown above when viewed as a circuit component. Identical parts are given the same numbers and explanations will be omitted. In the figure, LUT represents a circuit block consisting of a look-up table, and MA represents a circuit block consisting of an arithmetic unit. In this way, each block is intricately intertwined, making it unavoidable to increase complexity, increase costs, and reduce reliability.

The present invention has been made in view of the above-mentioned problems, and its primary purpose is to realize an image signal processing device suitable for compactness and weight reduction by commonizing and integrating individual blocks. .

(Means for Solving the Problems) The present invention for solving the above problems includes: a single memory configuring a lookup table for image signal processing; a calculation means for performing calculations for image signal processing; Feedback means is provided for connecting the respective outputs and inputs of the memory and the arithmetic means, and the image signal processing is performed by the memory and the arithmetic means a plurality of times through the feedback means. It is characterized by the following.

(Operation) In the image signal processing device of the present invention, image signal processing is performed by loop processing a plurality of times in the memory and the calculation means via the feedback means.

(Example) Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a configuration diagram showing an example of the configuration of an embodiment of the present invention. In the figure, 20 is a large capacity memory lookup table (hereinafter simply referred to as lookup table).

This lookup table 20 has NMAX number of LUTs.
It consists of a single large-capacity memory capable of processing. Then, this lookup table 20 contains the bandwidth compression, U
The parts that perform SM and gradation processing are integrated. Then, address specification from outside, data I/
O, R/W is possible.

21 is a computing unit. This arithmetic unit 21 is N IMA
It is an arithmetic unit that can perform X operations (addition, subtraction, multiplication, division, and comparison operations). In this arithmetic unit 21, the parts that perform each process of primary color conversion, secondary color conversion, black generation, UCR, and USM are shared and integrated.

A, REG is an address register for specifying a memory address, I. REG is an input register for image input, D
, REG are bidirectional data registers for passing memory data in both directions, 0. REG is an output register for image output, O. BD is a unidirectional bus driver that drives the bus in one direction, Y. REG is a Y register for the Y input of the arithmetic unit 21; B. BD is a bidirectional bus driver that drives the bus in both directions. FB, REG is a feedback register for feedback, and this feedback register FB.REG is a feedback register for feedback. Feedback is performed NMAX times by REG. IX. BD is an X-person cab bus driver for the X input of the arithmetic unit 21, and FB. BD is a feedback bus driver for feedback, ADC.
BD is an address CTR bus driver.

The lookup table 20 and the arithmetic unit 21 as a whole operate on the feedback bus FB. A feedback loop is formed by the BUS.

The operation of this embodiment will be explained below. A single person capacity lookup table 20 is externally accessed from address register A.
．． The structure is such that internal data in the memory can be read and written by REG. Once the signal processing conversion curve for a certain image input is set, the address and data I
/O's gate is closed and I. O,RE for REG
Switch to G processing mode. Generally, the process of ■→0 is single, and if the function is [i, then 0=f i
(It+) Here, It+ is expressed by pixel information at a certain time t.

In this signal processing method, from t1 to t1+1 of a certain pixel information It+, t1.1-t. Setting the time Δt obtained by dividing -ΔT into N equal parts gives Δt - ΔT/N, and this Δt is taken as the minimum unit of processing time of the lookup table 20 and the arithmetic unit 21.

Then, calculate N times (f+, f2+ ..., fN) by Δ
In order to achieve this within T time, FB. R
To obtain O by inserting EG and executing loop processing, the following formula is used.

0=fN(fN-1...f+(It
+)...)) In this way, N for the input It,
The calculation processes f,, f2, . . . , fN are executed during Δτ.

FIG. 2 is a time chart schematically showing the process when the feedback process is performed N times.

In the figure, pixel (i.j) and pixel (i+1,j)
The area is mainly shown. For example, as the first process, band compression processing is performed using LUT. Do it at 20.

Then, the output data of LUT20 is transferred to the feedback bus FB. The data is returned to the MA 21 via the BUS, and the MA 21 performs primary color conversion processing as a second process. Next, MA2
The output data of No. 1 is returned to the MA 21 again via the feedback buses FB and BUS, and as a third process, a secondary color conversion process is performed in the MA 21. Then, such processing is repeated, and finally, gradation processing is performed in the LUT 20 as the Nth processing. In this way, by performing a series of N times of processing within the period of one pixel by loop processing using feedback, the circuit configuration can be extremely simplified.

FIG. 3 is a time chart showing an example of the state of each part during operation of the circuit shown in FIG. 1. In the figure, (a)
indicates the number of the horizontal scanning line in the vertical direction. (a) is the horizontal synchronization signal H. Indicates Sync. (
C) shows a pixel signal, and here shows the case where n pixels exist within one water early period. and,
The state of the i-th pixel among these n pixels is (
(English) The image is shown enlarged below. (E) is a scan signal, and scanning is performed when this scan signal is at a high level. (E) is an enlarged version of the pixel signal shown in (C) above. Therefore, this pixel is the (i, j)th pixel (first in the horizontal direction and jth in the vertical direction). (
power) is the input register ■. REG state, and (g) is the X-man Cabas Driver IX. Indicates the status of the BD. (
h) is the state of the memory output of LUT20, (g) is the state of the feedback register FB, REG, (c) is the state of the feedback bus driver FB, BD, (sa) is the state of the address CTR bus driver ADC, BD, ( C) is the state of Y register Y, REG, (S) is the state of MA21 output, (C) is the state of output register O. REG status, (So)
indicates the state (mode) of the entire device.

That is, IX. When the BD becomes low level and data is input, processing is performed by the LUT 20. At this time, since the feedback bus drivers FB and BD are in the passing state, a feedback loop is formed, and 3
Processing (LOG conversion, HL-SD setup, preliminary Q
) is carried out.

Similarly, MA21 performs three processes (primary color conversion,
(primary force splitter, secondary color splitter). Then, three processes (limiter, level adjustment, preliminary) are performed in the LUT 20 again. And similarly M
A21 also requires three processes (secondary color conversion, UCR-UCA,
color composition) is performed. And finally, process 3 times with LUT20 (gradation, dot out, bit conversion)
will be held. Here, output register 0. REG enters the passing state, and the processed data is output to the outside as an image output.

In the above explanation, processing was performed 15 times, but since feedback loop processing was used, the circuit was
20, MA21, and a feedback bus. Note that the number of times of processing and the contents of processing are not limited to those described above.

(Effects of the Invention) As explained in detail above, the present invention uses a lookup table, an arithmetic unit, and a feedback bus,
Signal processing for one pixel is performed using feedback loop processing. Therefore, by sharing and integrating individual blocks, it is possible to realize an image signal processing device suitable for downsizing and weight reduction.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the state of signal processing of the present invention, and FIG.
Time chart showing the operating state of the circuit shown in the figure, No. 4
The figure is a block diagram showing the schematic structure of a conventional image signal processing device.
FIG. 5 is a block diagram showing another example of a conventional image signal processing device, and FIG. 6 is an explanatory diagram functionally showing the image signal processing device shown in FIG. 1... 1st block 2... 2nd block 3.
...i-th block 4...n-th block 11...
・Band compression circuit 12...Primary color conversion circuit 13...
・Black generation circuit 14...Secondary color conversion circuit 15...
・UCR circuit ゜ 16...USM circuit 17...
Gradation circuit 20...Large capacity memory lookup table 21...
・Arithmetic unit

Claims (1)

[Scope of Claims] A single memory constituting a lookup table for image signal processing, arithmetic means for performing arithmetic operations for image signal processing, and respective outputs and inputs of the memory and the arithmetic means. 1. An image signal processing apparatus, comprising: a feedback means for connecting a plurality of image signals, and is configured to perform image signal processing by loop processing a plurality of times in the memory and the calculation means via the feedback means.