JPH02237062A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable the reduction of a memory cell in size by a method wherein a diffusion preventive layer is formed on a source and a drain diffusion layer which are both partially exposed and a first conductive layer. CONSTITUTION:A source and a drain diffusion layer 13 are formed, an insulating film 17 of oxide film is deposited on the whole face, and a contact hole 20 is bored in the insulating film 17. The contact hole 20 is so formed as to make the surface of the source.drain diffusion layer 13 and a part (dimension: d) of a conductive layer 16 exposed. A low resistive second conductive layer 19 of tungsten W is selectively grown on the exposed surfaces of the source.drain diffusion layer 13 and the first conductive layer 13. A second thick poly-silicon film is deposited thereon, which is etched so as to remain on the second conductive layer 19 to form a high resistive load layer 18. By this setup, a low resistive load region is not required to be formed on the second poly-silicon film through an ion implantation method or the like and a high resistive load region does not become narrow, so that a memory cell can be reduced in size.

Description

[Detailed Description of the Invention] [Summary] Regarding the improvement of a semiconductor device manufacturing method, particularly a semiconductor device having a highly integrated semiconductor memory cell of a static type RAM, the size of the memory cell can be reduced and the size of the SRAM can be increased. In order to provide a suitable method for manufacturing a semiconductor device, in an SRAM cell, a step of forming an IN-th conductive layer, a step of forming a source/drain diffusion layer using the first conductive layer as a mask, and the like. , thereafter [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, particularly a static type R
AM (hereinafter referred to as S R A M (Static Ra
The present invention relates to improvements in semiconductor devices having highly integrated semiconductor memory cells (called dom^access memory).

[Conventional technology]

Among semiconductor memories, SRAM is a memory that can read and write data at any address in the same cycle time, and retains data as long as a predetermined power supply voltage is maintained. The memory cell of this SRAM includes, for example, a flip-flop composed of two inverters and two switching transistors for connecting the flip-flop and a bit line. There are various types of flip-flops that make up this memory cell, but the high-resistance load type that uses polysilicon resistors as the load of the inverter can be formed by stacking this polysilicon resistor on top of the MOS transistors. The cell size can be reduced, making it suitable for miniaturization and high integration. 7 is a plan view of a conventional memory cell, FIG. 8 is a sectional view taken along the line A-A" in FIG. 7, and FIG. 9 is a partially enlarged sectional view of FIG. The load method is shown.

In the plan view of FIG. 7, Q. , Qt are switching transistors, and the polysilicon layer forming the gate electrode thereof becomes a word line (11L). Also, Q, ,Q
．． is the drive transistor of the inverter. The high resistance load region is formed by the second polysilicon layer (the area surrounded by the dotted line in the figure), and the portions of this second polysilicon layer other than the high resistance load region are doped with impurities to reduce the It is used as a resistance region and as wiring within a memory cell.

The power wiring is formed from the second polysilicon layer, and the grounding wiring is diffused! (area surrounded by a dashed line in the figure).

In the cross-sectional views of FIGS. 8 and 9, for example, a p-type well is formed on an n-type substrate 61, and an n-type MOS for a memory cell is formed in this well. That is, 6
2 is an oxide film for element isolation, 63 is a source/drain diffusion layer, 64 is a gate oxide film, 65 is a gate electrode, and 66 is a first
67 is an insulating film; 68 is a second polysilicon layer consisting of a high resistance load region 69 and a low resistance region 70; In order to make contact between the source/drain diffusion layer 63 and the first polysilicon layer 66, the IJ68 is ion-implanted only in this contact SM region (for example, As+ is implanted as an impurity ion at an energy of 60 KeV and a dose of 8E15 cm-2). A low-resistance region 70 is formed by implantation under certain conditions, and the other regions are high-resistance load regions 69. In the figure, dimension d indicates a contact portion between a first conductive layer 66 made of a first polysilicon layer and a second polysilicon layer 68. In the figure, 71 is an aluminum (Aj) wiring, and 72 is a protective film. The memory cell having the above configuration has an equivalent circuit diagram of a high resistance load type shown in FIG.

[Problem to be solved by the invention]

In the conventional SRAM memory cell, since the high resistance load region 69 and the low resistance region 70 are formed in the second polysilicon layer 68, there are the following problems.

(2) Due to various heat treatments after ion implantation, impurity ions were laterally diffused from the low resistance region 70 side to the high resistance load region 69 side, narrowing the effective load resistance range. For this reason,
In order to secure a sufficient high-resistance load region 69, a length that takes into account lateral diffusion is required, which has been an obstacle to miniaturization of memory cells.

(2) Since the contact region (low resistance region 70) does not function as a resistor, the effective load region is limited. This has made it difficult to miniaturize memory cells.

Therefore, the present invention can reduce the size of the memory cell, and the SRA
The purpose of this paper is to provide a method for manufacturing semiconductor devices suitable for high integration of M. [Means for Solving the Problems] The above problems include, in an SRAM cell, a step of forming a first conductive layer, a step of forming a source/drain diffusion layer using the first conductive layer as a mask, forming an insulating film over the entire surface, opening a part of the insulating film and exposing a part of the source/drain diffusion layer and the first conductive layer; Achieved by a method for manufacturing a semiconductor device, comprising the steps of forming a diffusion prevention layer on a first conductive layer, and forming a high resistance load layer covering all or part of the diffusion prevention layer. Ru.

[Effect]

According to the present invention, in order to connect the source/drain diffusion layer and the first conductive layer, a diffusion prevention layer is formed directly or through a low resistance polysilicon layer, and a high resistance load is placed on the diffusion prevention layer. By forming the layer, the high resistance load region can be arranged larger than in the past, and the memory cell size can be reduced, contributing to higher integration of SRΔM. [Example] Hereinafter, the present invention will be specifically explained using an illustrated example.

FIG. 1 is a sectional view of a memory cell portion of a first embodiment of the present invention.

In the figure, 11 is a substrate, 12 is an oxide film for element isolation,
13 is a source/drain diffusion layer, l4 is a gate oxide film,
15 is a gate electrode formed from a first layer polysilicon layer, 16 is a first layer conductive layer made of the same first layer polysilicon film, 17 is an insulating film, and 18 is a second layer polysilicon film. A low-resistance second-layer conductive layer 19 is formed on the surface of the source/drain diffusion layer 13 and the first-layer conductive layer 16 below the high-resistance load layer 18.

FIGS. 2(a) to 2(e) are cross-sectional views of the manufacturing process of the memory cell portion of the first embodiment of the present invention. Note that parts corresponding to those in FIG. 1 are denoted by the same reference numerals (the same applies to other embodiments described below). First, as shown in FIG. 2A, a p-type well is formed on an n-type substrate 11, and an oxide film 12 for element isolation is formed in this well using a selective oxidation method or the like. A gate oxide film l4 is formed, and then a 2000-m thick film is formed on the entire surface.
A first layer polysilicon film having a thickness of approximately 3000 nm is deposited and patterned to form a gate electrode 15 and a first conductive layer 16. Next, as shown in FIG. 3B, after ion implantation of As'' as an impurity is performed under the conditions of an energy of 60 KeV and a dose of 8E15 cm-'', a source/drain diffusion layer 13 is formed by heat treatment.

Next, as shown in FIG. 2C, an oxide film (S
(i) is deposited to a thickness of about 4,000 to 5,000 layers, and a contact hole 20 is opened in this insulation layer 1!17. This contact hole 20 exposes the surface of the source/drain diffusion layer 13 and a part of the lNth conductive layer 16 (
It is formed so that dimension d) is exposed.

Next, as shown in FIG. 3B, a low-resistance second conductive layer 19 made of, for example, tungsten (
W) is selectively grown to a film thickness of about 500 to 1000 layers. This 235th conductive layer 19 functions as a diffusion prevention layer. At this time, the selective growth conditions for W are tungsten hexafluoride (WF &) and monosilane (Si
A one-step method is used in which Hm) gas is reacted to grow -, or a two-step method is used in which the ridges are reacted with silicon (St) on the substrate and then reduced with hydrogen gas. Next, as shown in the same figure (e), 2000 to 30
Deposit a second layer of polysilicon film with a thickness of about 0.00 mm,
This second layer polysilicon film is etched to remain on the second layer conductive layer 19 to form a high resistance load 1i18. For the following steps, normal steps for manufacturing SRAM cells are used.

According to the memory cell of the first embodiment, selectively grown W
The second conductive layer 19 is a source/drain diffusion layer l3.
and the first conductive layer 16, and at the same time the second conductive layer 16.
It is connected to the second conductive layer l9 of the polysilicon film. Therefore, it is not necessary to form a low resistance load region in the second layer polysilicon film by ion implantation or the like as in the conventional method.

Further, the high resistance load region is not sacrificed in the contact region portion, and at the same time, since there is no lateral diffusion due to heat treatment or the like, the high resistance load region does not become narrow. Therefore, the size of the memory cell can be reduced, and miniaturization and high integration of the SRAM can be achieved. For example, the length of the conventional second layer polysilicon film is 8μ, of which the contact portion is 3μ.
However, according to this embodiment, this can be reduced by 3 .mu.m, and the length of the second layer polysilicon film can be reduced to 5 .mu.m.

Furthermore, in this embodiment, since the second conductive layer Nl9 is formed by selective growth of W, the number of photolithography steps can be reduced by one. FIGS. 3(a) and 3(b) are cross-sectional views of the manufacturing process of the memory cell portion of the second embodiment of the present invention. First, after going through the same manufacturing steps (a) to (C) as in the first embodiment, as shown in FIG. Then, as shown in FIG. 3(b), the W film 21 is patterned to form a second conductive layer N22, and then
A second polysilicon film is deposited and etched to form a high resistance load layer 23. FIGS. 4(a) and 4(b) are cross-sectional views of the manufacturing process of the memory cell portion of the third embodiment of the present invention. First, after going through the same manufacturing steps (a) to (C) as in the first embodiment, as shown in FIG. WWl4, which will become the layer 32, is deposited by a sputtering method or the like, and then, as shown in the third figure, a polysilicon layer 31 and a second conductive layer 32 are deposited.
After patterning, a second layer polysilicon film is deposited and etched to form a high resistance load layer 33. According to the memory cells of the second and third embodiments, the second M
A high resistance load layer 2θ, 33 is formed on the conductive layer N22, 32, and the size of the memory cell can be reduced as in the first embodiment, and miniaturization and high integration of the SRAM can be achieved.

FIG. 5 is a sectional view of the manufacturing process of the memory cell portion of the fourth embodiment of the present invention.

The memory cell of this example is manufactured using the manufacturing process (a) of the first example.
) to (C), a polysilicon layer 41 is buried in the contact hole 20 above the source/drain diffusion layer l3, and this polysilicon layer 41 is subjected to a process to reduce the resistance. Such embedding of polysilicon [41] is performed, for example, by depositing a polysilicon layer over the entire surface and then etching back. Next, a W film is selectively grown on the exposed surfaces of the polysilicon layer 41 and the first conductive layer 16 to form a second conductive layer 42 that serves as a diffusion prevention film, and then a second conductive layer 42 is formed as a diffusion prevention film. A high resistance load layer 43 is formed by depositing a silicon film.

FIG. 6 is a sectional view of the manufacturing process of the memory cell portion of the fifth embodiment of the present invention.

In the memory cell of this example, after forming buried polysilicon N41 in the same manner as in the fourth example, a W film is deposited by sputtering or the like, a second conductive layer [51 is formed by buttering, and then a second conductive layer [51] is formed by patterning. A second layer polysilicon film is deposited to form a high resistance load N52.

According to the memory cells of the fourth and fifth embodiments, the size of the memory cell can be reduced as in the first embodiment, and miniaturization and high integration of the SRAM can be achieved. Furthermore, in these embodiments, by forming the buried polysilicon layer 41,
The level difference can be made gentle, making microfabrication easier. Furthermore, in the fourth embodiment, since the polysilicon layer 41 is formed by etching back and the W film is selectively grown, the number of masks can be reduced and the process can be shortened.

In each of the above embodiments, a W film was used as a diffusion prevention film, but the scope of application of the present invention is not limited to this. For example, molybdenum (MO), titanium (Ti), cobalt (C)
o), metal film such as nickel (Ni), tantalum (Ta), or metal silicide (WSi, MoSiz, T
iSiz, etc.) or metal nitride (TiN, etc.), as long as it prevents impurity diffusion. For example, WSi is formed by depositing W and then subjecting it to heat treatment to react with Si.

〔Effect of the invention〕

As explained above, according to the present invention, in order to connect the source/drain diffusion layer and the first conductive layer, the second conductive layer, which serves as a diffusion prevention film, is formed directly or through a low resistance polysilicon layer. By forming the layer, the high resistance load region can be arranged larger than conventionally, and the memory cell size can be reduced, which has the effect of contributing to higher integration of SRAM.

[Brief explanation of drawings]

FIG. 1 is a sectional view of the memory cell portion of the first embodiment of the present invention, FIGS. 2(a) to (e) are sectional views of the manufacturing process of the memory cell portion of the first embodiment of the present invention, and FIG. 3(a) ) and (b) are sectional views of the manufacturing process of the memory cell portion of the second embodiment of the present invention, FIGS. 4(a) and b) are sectional views of the manufacturing process of the memory cell portion of the third embodiment of the invention, and FIG. FIG. 6 is a sectional view of the manufacturing process of the memory cell portion of the fourth embodiment of the present invention, FIG. 6 is a sectional view of the manufacturing process of the memory cell portion of the fifth embodiment of the present invention, and FIG. 7 is a plan view of a conventional memory cell. 8 is a cross-sectional view taken along the line AA' in FIG. 7, FIG. 9 is a partially enlarged cross-sectional view of FIG. 8, and FIG. 10 is an equivalent circuit diagram of a high resistance load type memory cell. 17 is an insulating film, 18, 23, 33, 43, 52 are high resistance load layers, 20 is a contact hole, 21 is a W film, and 3l and 41 are polysilicon layers. Patent applicant Fujitsu Limited

Claims (6)

[Claims] (1) In an SRAM cell, a step of forming a first conductive layer (16), a step of forming a source/drain diffusion layer (13) using the first conductive layer (16) as a mask, and An insulating film (17) is formed on the insulating film (17), a part of the insulating film (17) is opened, and the source
A step of exposing a part of the drain diffusion layer (13) and the first conductive layer (16), and forming a diffusion prevention layer on the exposed source/drain diffusion layer (13) and the first conductive layer (16). a step of forming a high resistance load layer (1) covering all or part of the diffusion prevention layer;
8) A method for manufacturing a semiconductor device, comprising the step of forming. (2) The step of forming the diffusion prevention layer includes the exposed source/drain diffusion layer (13) and the first conductive layer (
16) The method of manufacturing a semiconductor device according to claim 1, further comprising forming a second conductive layer (19, 22) thereon. (3) The step of forming the diffusion prevention layer includes the exposed source/drain diffusion layer (13) and the first conductive layer (
16) After forming a low resistance polysilicon layer (31) on the polysilicon layer (31), a second conductive layer (32) is formed on the polysilicon layer (31).
2. The method of manufacturing a semiconductor device according to claim 1, wherein: (4) The step of forming the diffusion prevention layer includes burying a low resistance polysilicon layer (41) on the exposed source/drain diffusion layer (13), and then
) and the second conductive layer (4) on the first conductive layer (16).
2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of forming: 2, 51). (5) The second conductive layer (19, 22, 32, 42, 5
Claim 2, 3 or 4, wherein 1) is any one of W, Mo, Ti, Co, Ni, an alloy thereof, or a silicide or nitride compound thereof. A method for manufacturing a semiconductor device. (6) The high resistance load layer (18, 23, 33, 43, 5
2. The method of manufacturing a semiconductor device according to claim 1, wherein 2) is a non-doped polysilicon layer.