JPH02237158A - Semiconductor device and its manufacture - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The semiconductor device and method of manufacturing the same of the present invention relate to an N1oS transistor using element isolation using a trench filling method that allows for high integration, and a method of manufacturing the same.

2. Description of the Related Art In recent years, there has been an increasing trend toward miniaturization of semiconductor devices in order to achieve higher integration. Further, element isolation is also required to be miniaturized, and it is necessary to develop a semiconductor device using element isolation using a trench filling method.

A semiconductor device using the conventional trench filling method for element isolation will be described with reference to FIGS. 5 and 6.

FIG. 5 is a cross-sectional view of an N-channel MOS} transistor, in which (a) is a cross-sectional view in the xx' direction shown in FIG. 4, and (b) is a cross-sectional view in the Y-Y' direction. It is. In FIG. 5, a groove is formed in an element isolation region on a P-type substrate L, and boron (B) ions are implanted into the bottom of the groove to form a p-region θ for channel stop. Next, an LP-CVD oxide film 2 is deposited to fill the trench, and then planarized by etching back or the like.

In the following, similar to a well-known MOS transistor, a p-region 4 for controlling the threshold voltage of the transistor is formed, a gate oxide film 5 and a gate electrode 6 are formed, and the short channel effect of the transistor is prevented. In this method, an n region 8' is formed, a CVD oxide film 7 is formed as a sidewall, and an n♦ region 8 is formed as a source/drain.

FIG. 6 is also a cross-sectional view of an N-channel MOS transistor, in which (a) is a cross-sectional view in the x-x' direction shown in FIG. 4, and (b) is a cross-sectional view in the Y-Y' direction. be. In FIG. 6, a trench is formed in the element isolation region on the P-type substrate 1, and boron (B) ions are implanted into the bottom and side surfaces of the trench to form a p-region 9' for channel stop. Next, LP-C
After depositing a VD oxide film 2 to fill the trench, it is planarized by etching back or the like. In the following, similar to a well-known MOS transistor, a p-region 4 for controlling the threshold voltage of the transistor is formed, a gate oxide film 5 and a gate electrode 6 are formed, and the short channel effect of the transistor is prevented. n-region 8' and n which becomes the source/drain.
◆A region 8 is formed.

Problems to be Solved by the Invention However, the above-mentioned conventional semiconductor devices still have the following problems.

■ In the semiconductor device shown in Figure 5, when the gate width W (the width of the active region in the Y-Y' direction in Figure 4) is approximately 3 μm or less, a drain current flows near the shoulder of the trench when a gate voltage is applied. A parasitic MOS transistor is formed.

This parasitic MOS transistor has a lower threshold voltage than a normal transistor and affects the original transistor characteristics.

For example, when the gate width W is 3 to 2 μm, a normal MOS transistor and a parasitic MOS transistor are connected in parallel, and a hump phenomenon is observed in the drain current with respect to the gate applied voltage. In addition, if the thickness is less than 2 μm, parasitic MOS
}The transistor becomes dominant, and the apparent threshold voltage decreases. Therefore, it is very difficult to make the threshold voltage constant when simultaneously fabricating MOS transistors having different gate widths. Further, since the characteristics of the above-mentioned parasitic MOS transistor are influenced by the shape of the groove shoulder, it is very difficult to stabilize the threshold voltage.

■ In order to solve the problem described in the above-mentioned problem (■), the semiconductor device shown in FIG.
Although the influence of the parasitic MOS transistor can be suppressed by forming a p region 9' near the shoulder of the trench and increasing the threshold voltage near the shoulder, the n1 region forming the source and drain regions can be suppressed. Since n4 region 8 and p region 9' are in contact with each other at a high concentration, as the concentration of n4 region 8 and p region 9' on the trench sidewall increases, the reverse leakage current at the PN junction increases and the withstand voltage decreases. That is, when a voltage is applied to the source (or drain), a current flows from the n-region 8 to the p-region 9', and from the p-region 9' to the P-type substrate. Moreover, when the concentration of n-region 8 is lowered.
The resistance of the n◆ region 8 increases, deteriorating the characteristics of the element, and also deteriorating the contact with wiring to be formed later. moreover,
If the concentration of p-region 9' is lowered, the generation of parasitic MOS transistors cannot be suppressed, so it is difficult to reduce leakage current.

Means for Solving the Problems In order to solve the above problems, the present invention forms a structure in which at least a trench in an element isolation region is filled with an insulating material for insulation isolation in a semiconductor substrate, and a structure is formed in the upper part of the side wall of the trench in the element isolation region. It has an impurity diffusion layer of the same type as the semiconductor substrate, and has a structure in which there is no impurity diffusion layer or a low concentration impurity layer at the bottom of the trench sidewall of the element isolation region, and is similar to a well-known MOS transistor. The structure includes an impurity diffusion layer in the source/drain region, a gate oxide film, a gate electrode, etc. to suppress the generation of parasitic MOS (parasitic MOS) lunges and stars, reduce reverse leakage current at the PN junction, and improve breakdown voltage.

In the present invention, an impurity diffusion layer of the same type as the semiconductor substrate is formed in the upper part of the trench sidewall of the element isolation region, and a structure in which the impurity diffusion layer is not present or has a low concentration is formed in the lower part of the trench sidewall, thereby forming the trench shoulder. The generation of parasitic MOS transistors is suppressed by increasing the threshold voltage at the transistor. At this time, an impurity diffusion layer is not formed in the lower part of the trench sidewall, or even if it is formed, it is at a low concentration, so that the concentration is low in the area in contact with the high concentration region of the impurity diffusion layer in the source/drain region, thereby preventing leakage at the PN junction. This can prevent deterioration of pressure resistance and pressure resistance.

EXAMPLES Below, a semiconductor device and a method for manufacturing the same according to the present invention will be explained with reference to the drawings.

(First Embodiment) FIG. 1 is a sectional view for explaining a first embodiment of a semiconductor device of the first invention, and an N-channel MOS transistor will be explained. (a) is x-x shown in Figure 4.
FIG. 3B is a cross-sectional view in the Y-Y′ direction; FIG. In FIG. 1, a trench is formed in an element isolation region on a P-type substrate 1, and boron (B) ions are implanted into the bottom of the trench to form a p-region 9 for channel stop. Next, LP-
After depositing a CVD oxide film 2 to fill the trench, it is planarized by etching back or the like. Next, in order to increase the threshold voltage at the groove shoulder, boron (B) ions are implanted into the upper part of the groove sidewall to form a p region 3. In the following, similar to a well-known MOS transistor, a p-region 4 for controlling the threshold voltage of the transistor is formed, a gate oxide film 5 and a gate electrode 6 are formed, and the gate oxide film 5 and the gate electrode 6 are formed to prevent the steep channel effect of the transistor. CV which becomes n-region 8' and sidewall
A D oxide film 7 and an n♦ region 8 which becomes a source/drain are formed.

(Second Embodiment) FIG. 2 is a sectional view for explaining the second embodiment of the semiconductor device of the first invention, which is almost the same as the first embodiment, and (a) is a cross-sectional view for explaining the second embodiment of the semiconductor device of the first invention. It is a cross-sectional view of the X-X' direction shown in a figure, and (b) is a cross-sectional view of the Y-Y' direction.

In FIG. 2, a groove is formed in the element isolation region on the P-type substrate 1,
Boron (B) ions are implanted into the groove bottom to form a p region 9 for channel stop. Next, the inside of the trench is oxidized to form an oxide film 2', and then poiySi 20 is deposited to fill the trench. After that, it is planarized by etching back or the like to form an oxidized PIX2'' on the upper part of the groove.Next, in order to increase the threshold voltage at the groove shoulder, boron (B) is ion-implanted into the upper part of the side wall of the groove to form a p region 3. .The following steps are similar to well-known MOS transistors, in which a p-region 4 for controlling the threshold voltage of the transistor is formed, a gate oxide film 5 and a gate electrode 6 are formed, and in order to prevent the short channel effect of the transistor. An n1 region 8'', a CVD oxide film 7, and an n1 region 8, which becomes a source and a drain, are formed.

(Third Embodiment) FIG. 3 is a process sectional view for explaining a third embodiment of the method for manufacturing a semiconductor device according to the second invention, and an N-channel MOS transistor will be described. Figure 3(a)~
(f) is a cross-sectional view along the Y-Y' direction shown in FIG. 4, and (g) to (h) are cross-sectional views along the X-X' direction.

Oxidize the P-type (100) silicon (Si) substrate 1 to become the base! Polysilicon (50 nm) 10 was formed as a thin film to serve as an etching stopper.
CVD oxide film 12 that forms Si) IK (300 nm) 1 and serves as an etching mask during Si etching.
A resist (1 μm) 13 is formed on the active region by photolithography.
(FIG. 3a) Next, using the resist 13 as an etching mask, the CVD oxide film 12 and the pol)'St film 11 and the oxide film 10 are anisotropically etched by dry etching, the resist 13 is removed, and the CVD oxide film 12 is removed. Using as an etching mask, the P-type substrate 1 is anisotropically etched by dry etching. groove 100 (depth 800 mm) in the element isolation region.
A CVD oxide film 14 is formed on the entire surface, and a C
The CVD oxide film 14 is anisotropically etched by dry etching to leave the CVD oxide film 14 on the trench sidewall, and boron (B) is implanted using the CVD oxide film 12 and the CVD oxide film 14 as an ion implantation mask to form a channel stop. A p-region 3 is formed for use. (FIG. 3b) Next, the CVD oxide film 12 and the CVD oxide film 14 are removed by wet etching or the like. At this time, the oxide film 10 is C
Because it is covered with the VD oxide film 14, the CVD oxide film 14
It will not be etched unless it is etched, so there is almost no side etching. (Figure 3C
) Next, a CVD oxide film (1 μm) 2 is deposited on the entire surface to fill the groove, and then it is flattened by etching back and a CVD oxide film (1 μm) 2 is deposited on the entire surface.
D oxide film 2 is left. Polysi film 1 during etchback
1 serves as an etching stopper, so over-etching is performed by about 150 nm so that the I) olYsi film 11 is completely exposed. (Figure 3d) Next, if B is ion-implanted so that the ion-implantation depth is about 300 nm, polyS i[1
1 serves as an ion implantation mask and is not implanted, but since the groove shoulder is thinner than 300 nm, B is implanted to form the p region 3. (FIG. 8e) Next, after selectively removing the polysl film 11, the oxide film 10 is removed, and B is ion-implanted for threshold voltage control to form the p-region 4, and the gate oxide film 5 and A gate electrode 6 is formed. (Fig. 3 f and g) Next, using the gate electrode 6 as an ion implantation mask, phosphorus (P) is used as an ion implantation mask.
) is ion-implanted to form an n region, a CVD oxide film 7 is formed on the entire surface, and the CVD oxide film 7 is anisotropically etched by dry etching to leave the CVD oxide film 7 on the side wall of the gate electrode 6. - Form n4 region 8 by ion-implanting arsenic (As) into the drain region. At this time, if the n◆ region 8 is formed deeper than the peak depth of the p region 3, the p region 3 is formed by ion implantation from the groove shoulder.
The B concentration at the N junction surface is low and does not cause leakage current or decrease in breakdown voltage. (FIG. 3h) Through the above steps, the semiconductor device shown in the first embodiment can be manufactured.

In the first to third embodiments, N-channel MO
S} Although I explained about the transistor, P channel MO
The same holds true for transistors. Furthermore, in the third embodiment, it was described that grooves were formed on the P-type substrate using the CVD oxide film 12 as an etching mask, but in this case, the grooves were formed on the P-type substrate using the resist 13 as an etching mask without forming the CVD oxide film 12. Groove formation may also be performed. Also, before forming the p-region 9 for channel stop, the sidewalls of the CVD oxide film 14 were formed.
If a PSG (phosphorous doped glass) film is used and then selective removal is performed, or a CVD oxide film 12 is not formed, C
The VD oxide film 14 may not be formed, and the p region 9 may be formed by ion implantation at 0°. Also,
The explanation has been made using the polysilicon film 11 as an etching stopper, but it can be used as a stopper for etching back after filling the trench, or as an ion implantation mask when forming the p region 3. It is also possible to use aluminum (AI) or the like.

Effects of the Invention As described above, the semiconductor device and the method for manufacturing the same of the present invention provide the following effects.

■ By providing a highly concentrated impurity diffusion layer of the same type as the semiconductor substrate at the groove shoulder, the threshold voltage at the shoulder increases, and even when the gate width W is 3 μm or less, the influence of parasitic MOS transistors can be suppressed, making it possible to use different gate widths. It is possible to create a constant threshold voltage even in a MOS} transistor,
The stability of the characteristics is checked.

■Also, since the same type of high concentration impurity as the semiconductor substrate in ■ is only at the groove shoulder and not on the groove sidewalls, even if a different type of high concentration impurity diffusion layer is formed to form the source/drain region, the concentration will not be high. Since they are not in contact with each other, the reverse leakage current at the PN junction can be reduced and the device characteristics can be improved.

[Brief explanation of drawings]

FIG. 1 shows a semiconductor device of the first invention. A cross-sectional view for explaining the first embodiment, FIG. 2 is a cross-sectional view for explaining the second embodiment of the semiconductor device of the first invention, and FIG. 3 is a method for manufacturing the semiconductor device of the second invention. FIG. 4 is a top view for explaining the direction of the cross section, and FIGS. 5 and 6 are cross-sectional views for explaining the conventional semiconductor device. It is. 1...P-type substrate, 2...CVD oxide film, 3...p region, 4...p-type region, 5
...Gate oxide film, 6...Gate electrode, 7...CVD oxide film, 8...n''''
region, 9...p region, 10...oxide film, 11...1) olysi film, 12...CVD oxide film, 3... ...Resist.

Claims (2)

[Claims] (1) In a semiconductor substrate, at least a trench in an element isolation region is filled with an insulator to form an insulation isolation structure, an impurity diffusion layer of the same type as the semiconductor substrate is provided on an upper side wall of the trench in the element isolation region, and the element isolation A semiconductor device having a structure in which the region does not have an impurity diffusion layer or has a low concentration impurity layer at the bottom of the trench sidewall, and a source/drain region impurity diffusion layer, a gate oxide film, and a gate electrode of a MOS transistor are formed. . (2) forming an oxide film and a thin film as an etching stopper on one main surface of the semiconductor substrate at least over a region that will become an active region, and forming a groove in the semiconductor substrate in a region that will become an element isolation region; A step of forming a first impurity diffusion layer of the same type as the semiconductor substrate on the bottom surface of the trench, a step of burying the trench with an insulator or the like to form an element isolation region, and an etch-back process using the thin film serving as the etching stopper. and a step of implanting impurity ions of the same type as the semiconductor substrate using a thin film serving as an etching stopper on the active region as an implantation mask to form an impurity diffusion layer of the same type as the semiconductor substrate on the upper part of the trench side wall. Manufacturing a semiconductor device comprising the steps of removing a thin film serving as an etching stopper on the active region and the oxide film, and forming a gate oxide film, a gate electrode, and a source/drain region impurity diffusion layer of a MOS transistor. Method.