JPH0223748U - - Google Patents
Info
- Publication number
- JPH0223748U JPH0223748U JP10044788U JP10044788U JPH0223748U JP H0223748 U JPH0223748 U JP H0223748U JP 10044788 U JP10044788 U JP 10044788U JP 10044788 U JP10044788 U JP 10044788U JP H0223748 U JPH0223748 U JP H0223748U
- Authority
- JP
- Japan
- Prior art keywords
- circuit emulator
- emulator
- rom
- cpu
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000523 sample Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第1図は本考案に係る簡易インサーキツト・エ
ミユレータの全体の構成を示す図、第2図はRO
Mエミユレータ部の構成を示す図、第3図はマー
シヤリング・ボード部の入出力信号を説明するた
めの図である。
10…ROMエミユレータ部、11…コネクタ
、20…先端プローブ、21…CPU、30…マ
ーシヤリング・ボード部、40…インサーキツト
・エミユレータ本体。
Figure 1 is a diagram showing the overall configuration of a simple in-circuit emulator according to the present invention, and Figure 2 is a diagram showing the RO
FIG. 3 is a diagram showing the configuration of the M emulator section, and is a diagram for explaining input/output signals of the marshalling board section. 10... ROM emulator section, 11... connector, 20... tip probe, 21... CPU, 30... marshalling board section, 40... insert circuit emulator body.
Claims (1)
ROM領域をエミユレーシヨンすることができる
ROMエミユレータと、 CPUの端子の各信号をインサーキツト・エミ
ユレータ本体側に引き込むためのプローブとイン
サーキツト・エミユレータ本体の間に挿入され、
CPUからの信号の内、アドレス、データおよび
ステータス信号に分けてインサーキツト・エミユ
レータ本体側に送るマーシヤリング・ボード部と
、 バストレースを実現するために必要なトレー
ス・メモリ を具備した簡易インサーキツト・エミユレータ
。[Scope of claim for utility model registration] In an in-circuit emulator, it is inserted into the ROM socket of the target board,
It is inserted between the ROM emulator that can emulate the ROM area, the probe that pulls each signal from the CPU terminal into the in-circuit emulator body,
A simple in-circuit emulator that is equipped with a marshalling board that separates signals from the CPU into address, data, and status signals and sends them to the in-circuit emulator main body, and the trace memory necessary to realize bus trace.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10044788U JPH0223748U (en) | 1988-07-28 | 1988-07-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10044788U JPH0223748U (en) | 1988-07-28 | 1988-07-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0223748U true JPH0223748U (en) | 1990-02-16 |
Family
ID=31328526
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10044788U Pending JPH0223748U (en) | 1988-07-28 | 1988-07-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0223748U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01142947U (en) * | 1988-03-25 | 1989-09-29 |
-
1988
- 1988-07-28 JP JP10044788U patent/JPH0223748U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01142947U (en) * | 1988-03-25 | 1989-09-29 |
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