JPS647349U - - Google Patents
Info
- Publication number
- JPS647349U JPS647349U JP10075887U JP10075887U JPS647349U JP S647349 U JPS647349 U JP S647349U JP 10075887 U JP10075887 U JP 10075887U JP 10075887 U JP10075887 U JP 10075887U JP S647349 U JPS647349 U JP S647349U
- Authority
- JP
- Japan
- Prior art keywords
- target
- circuit
- connector
- microprocessor
- connects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本考案に係るＩＣＥの一実施例を示す
構成図、第２図は第１図における主要部分の詳細
な構成図、第３図は動作を説明するためのタイム
チヤートである。
１０……ターゲツト回路、１１……μＰソケツ
ト、１２……ターゲツトμＰ、２０……ＰＯＤ、
２１……コネクタ、Ａ，Ｂ，Ｃ……ポート・コネ
クタ、２２……サンプル・クロツク生成回路、３
０……外部プローブ、３１……外部プローブ・コ
ネクタ、４０……エミユレータ本体、４１……ト
レース・メモリ、４２……アドレス・カウンタ、
５０……ロジツク・クリツプ。
FIG. 1 is a block diagram showing an embodiment of the ICE according to the present invention, FIG. 2 is a detailed block diagram of the main parts in FIG. 1, and FIG. 3 is a time chart for explaining the operation. 10...Target circuit, 11...μP socket, 12...Target μP, 20...POD,
21... Connector, A, B, C... Port connector, 22... Sample clock generation circuit, 3
0...External probe, 31...External probe connector, 40...Emulator main body, 41...Trace memory, 42...Address counter,
50...Logic clip.
Claims (1)
サを対象とするインサーキツト・エミユレータで
あつて、 ターゲツト回路のロジツク・レベルをピツクア
ツプするためのロジツク・クリツプのコネクタ接
続が可能に形成された外部プローブと、 ターゲツト・マイクロプロセツサを搭載しター
ゲツト回路と接続してターゲツト回路を作動させ
ると共に、ターゲツト・マイクロプロセツサのＩ
／Ｏポートからターゲツト回路へ接続されるバス
・ラインに接続され前記外部プローブのコネクタ
の着脱が自在なポート・コネクタを配設したＰＯ
Ｄと を具備したことを特徴とするインサーキツト・エ
ミユレータ。[Claim for Utility Model Registration] An in-circuit emulator for a one-chip target microprocessor, which is formed to enable connection of a logic clip connector for picking up the logic level of the target circuit. It is equipped with an external probe and a target microprocessor, connects it to the target circuit, operates the target circuit, and connects the target microprocessor's I.
A PO that is connected to the bus line connected from the /O port to the target circuit and is equipped with a port connector that allows the connector of the external probe to be attached or detached.
An in-circuit emulator characterized by comprising D.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10075887U JPS647349U (en) | 1987-06-30 | 1987-06-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10075887U JPS647349U (en) | 1987-06-30 | 1987-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS647349U true JPS647349U (en) | 1989-01-17 |
Family
ID=31329128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10075887U Pending JPS647349U (en) | 1987-06-30 | 1987-06-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS647349U (en) |
-
1987
- 1987-06-30 JP JP10075887U patent/JPS647349U/ja active Pending
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