JPH02238517A - Picture data conversion circuit - Google Patents

Abstract

PURPOSE:To process the picture data at a high speed by using the coded data as an address to separate the picture data into the densities of three primary colors for production of the density data before the picture data is stored in a picture memory. CONSTITUTION:The hardware is added to decode data with no use of a CPU of a recording device after providing a logic arithmetic circuit before the picture data containing the encoded density information is sent to a picture memory 6. A decoding means consists of an S-RAM 5, a counter 4, and a data latch mechanism 2. For the inputted data, the picture codes are inputted to the lower rank addresses as the memory addresses of the S-RAM 5. At the same time, the higher rank addresses serve as the selection addresses of three primary colors and the output serves directly as the density data corresponding to the three primary colors. Thus the picture data is converted at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] In recent years, color images have become more precise, higher resolution, and full-color, and the amount of image data transferred to recording devices has become enormous. For this reason, in the past, image data separated into three primary colors was common, but as the amount of data has increased, image data in the form of coded compression has come to be handled on the HOST processing side. The present invention relates to a color recording device that records this coded image data.

[Summary of the invention]

In the image processing section of a color recording device that requires density information separated into three primary colors, the coded data is handled as an address before being stored in the image memory, and is used for decoding. The input address of the logic circuit is used as an input address, the calculation corresponding to this input address is performed, the data is separated into the densities of the three primary colors, and the output data is stored in the image memory as the density data of the three primary colors. If S-RAM is used, the input data will be the address of the RAM, and the output of the RAM will be the density data of each color.

[Conventional technology]

In order to process coded color image data, the density data of the three primary colors corresponding to the code is informed to the recording device before the image data is transferred.
Conventionally, a CPU mounted on the recording device side performs logical expansion based on this information. All encoded image data is once stored in memory, and prior to recording, the CPU retransfers it to the image memory based on the above-mentioned code correspondence information.

[Problem to be solved by the invention]

According to the above-mentioned conventional technology, since the decoding process of coded image data into the three primary colors covers all pixels, the processing time per pixel is determined by the processing capacity of the CPU installed in the recording device, and the image size is If it is large, this decoding time cannot be ignored compared to the entire recording time. Also, the encoded image data must be stored in memory, separate from the image memory area for the three primary colors.
It is necessary to secure the area. In addition, if you do not set up a separate area and use a sequence in which each pixel is processed as it is input and stored in memory while being converted to the three primary colors, the data transfer time to the recording device will be equivalent to the CPU processing time. As a result, the throughput of the system decreases.

[Means to solve the problem]

The present invention adds hardware for decoding the image data containing coded density information before transferring it to the image memory, saving the logic operation circuit and not using the CPU of the recording device. be. As a decoding means, one S-RAM. It consists of one counter and one data launch mechanism, and is possible with a simple hardware configuration. The input data is directly inputted as a memory address of the SRAM, and the image code is inputted to the lower address, and the upper address serves as the selection address for the three primary colors, and the output is the density data corresponding to each of the three primary colors. It goes without saying that it is necessary to transfer data for three primary colors to the image memory for one coat data input, but if the memory for the three primary colors is formatted, the data will be transferred three times. At this time, the upper address of the S-RAM changes in accordance with the color. In this way SRA
The conversion circuit using M has a very simple circuit configuration of 3 circuits, and since the data conversion time is determined by the S-RAM access time, the processing speed is extremely fast.

[Effect]

Since the decoding circuit is performed by dedicated hardware, the processing power of the CPU on the recording device side does not need to be a problem in processing the main image data.The processing speed is determined by the SRAM access time, so the CPU This allows for very high-speed data conversion.

In addition, since it is not necessary to store all image data in memory, it is possible to convert pixel by pixel and transfer it to the three primary color image memories, which not only requires extra memory area but also requires a fixed code. S-R if
It becomes possible to convert the AM into a ROM or a dedicated gate, and the peripheral circuitry becomes even simpler.

〔Example〕

Preferred embodiments of the present invention will be described below with reference to the drawings.

As shown in the block diagram of FIG. 1, this embodiment includes a laser chip 2 that temporarily secures input data 1, a ternary counter 4 that counts based on DMACLK (cross clock) generated by transfer to memory, and decoded data. It is composed of S-RAM 5 in which is written. In this example,
To explain the image data as a general 8-bit code, the code data has 256 values from 00h to FFh. In this case, the number of colors that can be expressed simultaneously is 356 colors, but the ratio of the three primary colors in each color is not expressed in this code, so the code that needs to be decoded, each of the 256 primary colors. The ratio is determined in advance by the host or the program running the system.
given to the recording device. For example, in an example where OOh is defined as pure white, the three primary colors are R (red) 100%, G (green) 100%, and B (blue) 100%.
If this is defined as bluish white, then R. G
This means that the ratio will be small. If the output data is multicolor 8-viso I- (256 tones), both are 100
% is the value of FFh. In other words, the input data is 00h
Therefore, the address of S-RAM is 00h,
Upper A8. A9 changes depending on the value of count 4 corresponding to the primary color of the output. Since the initial value is 00, if it is assumed to be R, the SRAM address indicating the R component corresponds to FIG. 7. Similarly, G can correspond to 8 and B can correspond to 9, and if the component ratios of the primary colors are different as described above, it is sufficient to change the data in the address. Also, as shown in the table, 80
If h is defined as gray, the proportion of each primary color will be 50%, so 80h will be output as S-RAM data.

In this example, transfer to table memory is performed in 8-bit units, so R
If this is transferred, Count 4 will amplify Count 1 by DMAC L K, and the upper address of S-RAM will indicate G. The code conversion for one pixel is completed by repeating the same sequence and performing memory transfer a total of three times. These timings are shown in FIG. In this example, the output is 8 bits, but of course a configuration in which the three primary colors are transferred to the image memory at the same time can also be considered.
In this case, the conversion process will be completed at once by transferring 24 bis once. Furthermore, the input code is not limited to 8 bits and 1 bits, but may also be 10 bits, which is 1024 colors at the same time, and a similar configuration is possible for many other bit numbers, and is not limited to this example. Also, S-RAM
The same applies to replacing ROM with ROM.

〔Effect of the invention〕

It goes without saying that the present invention makes it possible to process coded image data at high speed, has the effect of increasing the processing capacity of the recording device, and also improves the performance of the entire system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a data conversion circuit according to the present invention, and FIG. 2 is a timing chart showing the flow of data. 2...Data rasochi 4...Ternary count 5...S-RAM 6...Image memory or more Applicant Seiko Electronic Industries Co., Ltd. Agent Patent attorney Keinosuke Hayashi

Claims (2)

[Claims] (1) An image characterized in that, in a data conversion circuit in a recording device, a logical operation is performed on color image data having encoded density information before storing it in an image memory, and the data is separated into three primary color density data. Data conversion circuit. (2) The image data conversion circuit according to claim 1, further comprising a circuit for performing the logical operation using a dedicated memory.