JPH02238547A - Interruption control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding an interrupt control method in an information processing system in which a plurality of I/O adapters are connected to one CPU, a method is provided to ensure that interrupts from the I/O adapter to the CPU are performed. With the purpose of and an access flag that decodes the I/O adapter and provides a control signal to the interrupt control circuit indicating that the I/O adapter has been accessed, and while the I/O adapter is not being accessed, the access flag controls the interrupt. The circuit is configured to prohibit giving interrupts to the CPU.

[Industrial Field of Application] The present invention relates to an interrupt control method in an information processing system in which a plurality of I/O adapters are connected to one CPU via a bus.

There is an information processing system in which one CPU is connected to a plurality of 1/0 adapters via a bus. In this type of system, various types of I/O adapters are used.
O device is connected.

When a request is made to the CPU from the I/O adapter,
Issue an interrupt to the CPU. When the CPU receives an interrupt from the ■/0 adapter, it checks which adapter is issuing the interrupt, then checks the cause of the interrupt, and performs processing for the cause of the interrupt.

This allows the CPU to perform other processing even while waiting for an interrupt.

[Prior Art] FIG. 3 is a block diagram showing a conventional example. A CPU 1 and a plurality of I/O adapters 2 are connected via a bus 3. The inside of the I/O adapter 2 includes a register 2a that stores predetermined information from the CPUI, such as initial setting information, and an interrupt control circuit 2C that generates an interrupt signal to the CPU in response to an interrupt cause 2b. The I/O adapter 2 includes an input/output device (I/O) such as a file, etc.
4 is connected.

In a system configured in this way, after startup, the CP
After the UI performs its own preprocessing, etc., it performs settings for various I/O adapters 2. The preprocessing of the CPU herein refers to processing when the information processing system is started, such as setting initialization specific values of memory and registers, and creating jump tables for interrupt processing routines. Thereafter, the register 2a is accessed and initial information is set in the register 2a. I/
The O adapter 2 generates an interrupt via a control line when a request is generated to the CPUI after initialization is performed by the CPUI.

FIG. 4 is a diagram showing the acceptance state of interrupt processing. C.P.
Since the creation of the jump table for the interrupt processing routine has not yet been completed during the preprocessing period from the startup of U, no interrupts can be accepted during this period. On the other hand, when the adapter is set after the creation of the jump table for the interrupt processing routine is completed, it becomes possible to accept interrupts from the CPU.

[Problems to be Solved by the Invention] According to the conventional example described above, if an interrupt occurs due to some reason (for example, I/O adapter runaway, hardware abnormality, etc.) during the CPU preprocessing period, the interrupt will not be processed during this period. , the jump table for the interrupt processing routine has not been determined. In other words, an unexpected interruption occurs to the CPU, making it impossible for the CPU to continue normal processing.

Additionally, if a specific I/O adapter generates an interrupt due to a hardware error, etc., it is possible to disconnect the adapter using software, but interrupts must be prohibited, and multiple I/O adapters may If so, those interrupts are no longer available.

The present invention has been made in view of these problems, and it is an object of the present invention to provide an interrupt control method that can reliably perform interrupts from an I/O adapter to a CPU.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. Components that are the same as those in FIG. 3 are designated by the same reference numerals. In the figure, 2d
2e is an interrupt control circuit that generates an interrupt signal to CPU1 in response to interrupt cause 2b, and 2e is a register 2a from CPUUI.
Decode the address signal when accessing the I
This is an access flag that provides a control signal that does not issue an interrupt signal to the interrupt control circuit 2d while the /O adapter 2 is not being accessed.

[Operation] The I/O adapter 2 is cleared upon reset (initialization), and the access flag 2e outputs an interrupt prohibition signal to the interrupt control circuit 2d. Therefore, during this period, the cause of the interrupt is not receiving the interrupt request from the interrupt control circuit 2d due to some factor.
An interrupt to the CPUI will not occur even if it is given to . If the register 2a is accessed from the CPU 1, the access flag 2e decodes this address signal and knows that it has been accessed, and the interrupt control circuit 2
Give an interrupt enable signal to d. After this, it becomes possible to interrupt the CPU1. As described above, according to the present invention, an interrupt is given to the CPUI after the preprocessing of the CPU is completed and the jump destination address at the time of an interrupt is determined, so that a reliable interrupt is always possible.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. Components that are the same as those in FIG. 1 are designated by the same reference numerals. In the figure, 2f is an address decoder that decodes address data sent from the CPUI via bus 3;
Reference numeral g designates a JK flip-flop (hereinafter simply referred to as a flip-flop) which receives the decoded output of the address decoder 2f at its J input.

"0" is input to the K input of the flip-flop 2g, and the adapter reset signal is input to the reset input R. As the adapter reset signal, for example, a power-on reset signal or a system reset signal is used.

Further, the output of the address decoder 2f is input to the register 2a as an access signal.

2h is a 3-state buffer gate (hereinafter simply referred to as gate) which receives the output of flip-flop 2g as a control signal. The gate 2h outputs the interrupt signal from the interrupt cause 2b to the CPUI as an interrupt signal, and its output is controlled by the output of the flip-flop 2g.

The address decoder 2f and gate 2h in the figure correspond to the interrupt control circuit 2d in FIG. 1, and the flip-flop 2g corresponds to the access flag 2e in FIG. In the figure, I/O
Although only one adapter 2 is shown, it is assumed that a plurality of I/O adapters 2 are actually connected to the bus 3. The operation of the circuit configured as described above will be explained as follows.

First, when an adapter reset signal is input from the outside, the flip-flop 2g is reset and its output becomes "0". As a result, the output of gate 2h is prohibited. Therefore, even if an interrupt is input by mistake from interrupt cause 2b, the CP
It is not transmitted to the UI.

During this time, the CPUI performs its own preprocessing. At this preprocessing stage, a jump destination table for the interrupt processing routine is created.

Next, the CPUI outputs an address signal for accessing the target I/O adapter 2 and puts it on the bus 3.

Address decoder 2f decodes this address data. As a result, when detecting that its own I/O adapter has been selected, the address decoder 2f generates an access signal to access the register 2a. The CPUI will write data for adapter settings into the register 2a.

On the other hand, the flip-flop 2g is set by this access signal, and its output becomes "]-".

As a result, the output of gate 2h becomes enabled.

Therefore, when an interrupt signal is generated from interrupt cause 2b from now on, the interrupt is transmitted to the CPUI.

[Effects of the Invention] As described above in detail, according to the present invention, after the I/O adapter is reset, interrupts to the CPU are prohibited until the registers in the CPU adapter are accessed, thereby preventing the occurrence of unwarranted interrupts. Accordingly, it is possible to provide an interrupt control method that can prevent the above problems and reliably perform interrupts from the I/O adapter to the CPU. According to the present invention, since the occurrence of interrupts is prevented using hardware, it is possible to protect the system from unauthorized interrupts without changing conventional programs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a configuration block diagram showing an embodiment of the present invention; FIG. 3 is a block diagram showing a conventional example, FIG. 4 is a diagram showing the state of interrupt processing. In Figure 1, 1 is the CPU, 2 is an I/O adapter. , 2a is a register, 2b is the cause of the interrupt, 2d is an interrupt control circuit; 2e is the access flag, 3 is the bus, 4 is I/O.

Claims (1)

[Claims] In a system in which a plurality of I/O adapters (2) are connected to a CPU (1) via a bus (3), each I/O adapter (2) stores predetermined information. register (2a) to generate an interrupt signal in response to the interrupt cause (26), and
An interrupt control circuit (2d) that is provided to U (1), and a control signal that decodes the address when the CPU (1) accesses the register (2a) and indicates that the I/O adapter (2) has been accessed. The interrupt control circuit (
2d), and while the I/O adapter (2) is not being accessed, the access flag (2e) causes the interrupt control circuit (
2d) is configured to prohibit giving an interrupt to the CPU (1).