JPH02238657A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding semiconductor devices, the purpose of this invention is to prevent the analog part from malfunctioning even if an analog part and a digital part are formed in the same chip. At least one of the well region of the Hesink cell and the well region of the input/output cell is divided into a plurality of independent unit well regions, and at least a part of the divided unit well region group is grouped. Each of the well regions forms a digital part well region and an analog part well region, and the unit well regions within each group are configured to be interconnected only within the group.

[Industrial application field]

The present invention relates to a semiconductor device, and more particularly to the structure of a semiconductor chip in which an analog circuit and a digital circuit are simultaneously mounted on the same chip.

[Prior Art] Conventionally, semiconductor devices such as RC and LSI are generally manufactured separately into those for digital circuits and those for analog circuits. This is because the output signal in the digital section is likely to change, so when determining an intermediate level in the analog section, there is a risk that the constant voltage section present in the analog section will be affected and malfunction will occur.

In particular, as digital parts become faster and the number of output terminals increases, there is a problem in that output fluctuations become particularly large when these terminals are output simultaneously.

Therefore, as a general requirement, the idea of mounting a digital circuit section and an analog circuit section on one chip has been proposed for some time, but it has been difficult to put it into practical use as a practical matter.

One of the reasons for this is related to the above point, but the structure of conventionally commonly used semiconductor chips has wells for input/output cells on the chip 1, as shown in Figure 4. (t<ell) The 8N region 2 and the well regions 3, 3', 3'', . (In some cases, it consists of a well.) If a digital part circuit and an analog part circuit are mounted on such a chip at the same time, the power supply, that is, the well part, is common, so as mentioned above, power supply noise or There is a problem in that fluctuations affect analog parts such as amplifiers, etc., and until now it has not been possible to configure analog parts and digital parts on the same chip. Since the number of transistors installed in the device is limited, in order to realize the desire to separate and use some of them for digital use and the other part for analog use, we need to figure out how to efficiently separate the power supplies and avoid waste. There was a need for a technology that would allow the use of limited transistors.

[Problem to be solved by the invention]

The purpose of the present invention is to solve the above-mentioned conventional problems and provide a compact semiconductor device with high functionality that does not malfunction even at high speeds by simultaneously mounting and arranging a digital part circuit and an analog part circuit on the same chip. It is something to do.

[Means to solve the problem]

A semiconductor device according to the present invention employs the following technical configuration to achieve the above object. That is, at least one of the well region of the HESIC cell and the well region of the input/output cell formed in the same chip is divided into a plurality of independent unit well regions, and at least one of the divided unit well region groups is divided into a plurality of independent unit well regions. It is a semiconductor device in which the parts are grouped to form a digital part well region and an analog part well region, respectively, and the unit well regions in each group are connected by wiring only within the group.

In other words, in the present invention, as shown in FIG.
When forming the well region 3 that constitutes a basic cell including basic logic elements such as transistors and diodes, the well region is divided in advance into unit well regions of appropriate size. When forming the well region section 2 of the input/output cell section, as shown in FIG. It is also possible to divide the well regions 2 and 3 of both cell portions at the same time. In the present invention, the size and number of unit well regions in the well region of the HASIC cell row and the well region of the input/output cell section,
Although the arrangement form is not particularly limited, it depends on the requirements of the user, the size and number of logic cell units to be mounted, or the arrangement form and integration degree of the digital circuit section and analog circuit section as described later. It is determined as appropriate from the viewpoint that all cells can be used effectively without waste, such as maintenance of .

For example, the numerical values displayed in unit well regions B, -B8, etc. of the basic cell portion shown in FIG. 1 are examples of the number of basic cells provided in each unit well region.

Next, in the present invention, at least a part of the unit cell area divided as described above is grouped as a digital part well area D for use in a digital circuit, and at least a part of the remaining part is used for an analog circuit. The unit well area in the digital part well area D is connected only to other unit well areas in the area D by AI wiring, etc., and in the same way, the analog part well area The unit well regions in A are connected together.

In other words, the digital part well area D and the analog part well area A are completely separated in power supply, and the influence of noise occurring in the digital part is not transmitted to the analog part, so even analog circuit parts formed on the same chip can malfunction. There is no chance of it happening.

The method of dividing the digital part well area D and the analog part well area is not particularly limited, but can be determined by taking into consideration requirements from the user, functions required of the TC, LSI, etc. In the present invention, since the well region is formed in advance by subdividing into unit well regions, the above-mentioned division has considerable flexibility.

In the present invention, the unit well region can be easily manufactured using a normal diffusion process and an appropriate mask. Furthermore, after dividing the digital part well region D and the analog part well region A, wiring between unit well regions in each region can be realized by a method such as AI vapor deposition. In this wiring operation, wiring of the cells themselves can be performed at the same time. Note that these steps can be performed individually when applied to a custom cell, and a gate array may be used for a general-purpose product. Furthermore, both channel type and channelless type gate arrays can be used.

Next, in the present invention, the device of the present invention is completed by externally attaching a resistor or a capacitor necessary for analog operation to the circuit portion of the well region of the analog section.

On the other hand, as described above in the present invention, the power supply section for supplying the power supply voltage to the chip must be separated into at least one for the digital circuit section and one for the analog circuit section. The board is N
In the case of a type board, the board itself becomes VDD, so this is common, and VSS is separated for digital circuits and analog circuits. Further, if the substrate is P type, the substrate itself becomes 3s, so VDD must be isolated.

[For production]

In the present invention, when arranging a digital circuit section and an analog circuit section on the same chip, the basic cell section and the input/output cell section of the digital circuit section are connected to the input/output cell section of the analog circuit section. Since the cell part is completely separated, changes in the output signal and noise in the digital part do not affect the analog part, so malfunctions of the analog circuit part can be prevented. In addition, since the digital circuit section and the analog circuit section are arranged on one chip at the same time, the limited number of diodes and one helangistor can be used effectively without waste, making it possible to obtain a compact and highly functional semiconductor device at a low cost. Since the well region of the basic cell and the well region of the input/output cell are each formed in the unit well region in advance, the formation form of the analog part and the digital part can be arbitrarily adopted, so that the efficiency of gate usage rate can be increased. I can do it.

〔Example〕

One embodiment of the semiconductor device according to the present invention is shown in FIG.

FIG. 3 shows an example in which the technology of the present invention is applied to a C-MOS gate array, in which the substrate 1 is of N type and both the well region 2 of the input/output cell part and the well region 3 of the Gesink cell part are connected to the gate array. Unit well regions B, ~Ba shaped as shown in Figure 3
Divide each into

In this case, the basic configuration of the well portion is of P type. Also, a step of forming (:-MOS) is performed in the P-type well.

Next, the part A divided by the dotted line x-x' in FIG. Necessary parts of the unit well regions BIll+ BD2, . . . and BAI+, BA2, . At this time, wiring for forming logic elements in the basic cells of each unit well region is also performed at the same time. In this embodiment, since an N-type substrate is used, the isolated power supply is VSS.

〔effect〕

In the present invention, as a result of adopting the above configuration, the digital circuit section and the analog circuit section are formed on the same chip, and the semiconductor device has high functionality and accuracy that does not cause malfunctions due to noise in the digital circuit. Not only can a small, high-quality semiconductor device capable of performing various operations be obtained, but also limited transistors can be used efficiently and effectively, and the manufacturing method is simple, so the above-mentioned high-performance semiconductor can be obtained at a low cost.

Furthermore, since the composition ratio of the digital circuit section and the analog circuit section can be changed arbitrarily, it is possible to easily respond to the characteristics required by the user, and there is also the effect that the product can be completed in a short delivery time.

[Brief explanation of drawings]

FIGS. 1 and 2 are plan views showing an example of a well region dividing method according to the present invention. FIG. 3 is a plan view showing an embodiment of the semiconductor device of the present invention. FIG. 4 is a plan view showing the arrangement of well regions in a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Well area of input/output cell, 3.3', 3'', 3'''...Well area of basic cell row, 4...Wiring, A...Analog section Well region, D... Digital part well region, B1 to B6... Unit well region of basic cell row, B, to B,. ...Unit well area of input/output cell section, B
DI BD2... Digital unit unit well area, BA
I BA2...Analog part unit well area.

Claims (1)

[Claims] 1. At least one of the basic cell well region and the input/output cell well region formed in the same chip is divided into a plurality of independent unit well regions, and at least one of the divided unit well region groups 1. A semiconductor device, wherein parts of the semiconductor device are grouped to form a digital part well region and an analog part well region, respectively, and the unit well regions in each group are interconnected only within the group.