JPH0774252A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the area only of such regions of third wiring layers VDD, GND, formed on the chips of a semiconductor integrated circuit, as no transistor is formed thereunder. CONSTITUTION:Such regions as the signal line 5 of third wiring layer does not pass on a basic cell 10 are occupied entirely by VDD and GND wirings 6, 7 except the minimum wiring gap around the signal line 5 and the VDD and GND wirings 6, 7 are connected through a through holes 9 with the Vdd and GND wirings 3, 4 of a second wiring layer in the basic cell 10. This structure reduces the area occupied only by the VDD and GND wirings of third wiring layer under which no transistor is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, in the layout pattern design of a semiconductor integrated circuit, a required number of basic cells are prepared in advance by combining several transistors, and the basic cells are arranged and wired. The method to do is the mainstream.

An example of the basic cell will be described with reference to FIG. 4, which is a layout pattern diagram of an inverter logic basic cell. The wiring 11 is the VDD wiring of the second wiring layer, and the wiring 12 is the second wiring layer. This is the GND wiring.

The wiring 13 is a first wiring layer which serves as an input signal of the inverter, that is, a gate signal of the transistor. The wiring layer 14 is also a second wiring layer that serves as an input signal of the inverter, and the contact 15 is a contact that connects the first wiring layer and the second wiring layer.

The input signal of the inverter can be input in the first wiring layer 13 from the vertical direction of the basic cell as described above, or can be input from the left side in the second wiring layer 14.

A second wiring layer and a third wiring layer are formed on the second wiring layer 14.
It is also possible to arrange a through hole for connecting the wiring layers and to input through the third wiring layer.

The diffusion layers 16 and 17 are a P-type diffusion layer and an N-type diffusion layer, respectively. The contact 18 is a contact that connects the second wiring layer and the diffusion layer.

The wiring 19 is a second wiring layer which becomes an output signal of the inverter. The output signal of the inverter can be output on the right side of the basic cell as described above, or can be output by the third wiring layer by disposing a through hole on the second wiring layer 19.

The basic cell is usually provided with the input / output terminals of the respective wiring layers and the VDD and GND wirings 11 and 12 formed of the second wiring layer as described above.
2 is formed by connecting a transistor having a plurality of P-type and N-type diffusion layers and a gate.

Referring to FIG. 5 which is a layout pattern diagram of a semiconductor integrated circuit showing a conventional example using the above-mentioned basic cells, several kinds of basic cells 10 are divided into several columns and arranged side by side. Are connected by the first, second and third wiring layers to realize a predetermined circuit layout pattern.

Here, the contact 8 is for connecting the first wiring layer 1 and the second wiring layer 2, and the through hole 9 is for connecting the second wiring layer 2 and the third wiring layer 5. belongs to.

In the semiconductor integrated circuit, the VDD potential and the GND potential supplied from the VDD terminal and the GND terminal must be supplied to each transistor through the VDD wiring and the GND wiring.

Conventionally, the VDD wiring 6 and the GND wiring 7 are formed by the third wiring layer on the left and right sides of the arranged basic cells, and the second wiring layers 3, 4 are formed by the through holes 9.
It was realized by connecting to the second wiring layer of the basic cell in which they were arranged.

When the number of basic cells 10 arranged on the left and right is small, the VDD and GND wirings 3 and 4 of the second wiring layer are also short and the resistances of these wirings 3 and 4 are also small. Therefore, VDD and GND of the third wiring layer are small. As shown in FIG. 7, the wirings 6 and 7 may be provided on only one of the left and right sides. However, if the number of basic cells arranged on the left and right increases, VDD and GND may be increased by the third wiring layer as shown in FIG.
The wiring was put in several places.

The VDD wiring 6 of the third wiring layer connected to the VDD terminal 20 is on the outside and the GN of the third wiring layer is on the inside thereof.
The D wiring 7 is formed in two rectangular shapes. GND wiring 7
Is connected to the GND terminal 21. Sequence of basic cells 10
Are arranged inside the wiring 7.

Regarding wiring of signals other than VDD and GND, when the input / output terminal of each basic cell is a signal capable of inputting / outputting the same signal from a plurality of places as shown in FIG. 4, the layout area becomes small. Good terminals are selected and wired by each wiring layer 1, 2, 5 and contact 8 and through hole 9 as shown in FIG.

FIG. 6 shows the third wiring layers 5, 6 in FIG.
Only layout patterns 7 and 8 are shown.
Thus, the third wiring layer 5 passing over the basic cell 10
Between the signal wirings, there is a region where the wiring cannot pass though it can still be passed.

This vacant region has a small number of input / output signals but a large area of the basic cell, such as a large number of transistors forming the basic cell 10 or a large transistor which requires high drive capability. It increases even more when it is used frequently.

[0019]

In the above-described conventional semiconductor integrated circuit, the area where the wiring cannot pass though the wiring can still pass between the signal wirings of the plurality of third wiring layers passing over the basic cell. Exists, and conversely VDD, G of the third wiring layer
No transistor was formed under the ND wiring, and a region having only VDD and GND wiring was formed on the chip.

This is a factor that hinders the improvement of the integration degree of the semiconductor integrated circuit and increases the chip size.

The present invention solves the above problems.

[0022]

A semiconductor integrated circuit according to the present invention comprises a plurality of transistors provided on a semiconductor chip and at least three layers of first, second and third wirings insulated from each other by an interlayer insulating film. A semiconductor integrated circuit including a layer, a gate of a transistor is formed by the first wiring layer, and the plurality of transistors are connected by the first, second, and third wiring layers. Wiring layers are formed in directions orthogonal to each other, and between the plurality of wirings formed by the third wiring layer, V is provided in an empty area on the transistor through which the third layer wiring can further pass.
A feature is that a wiring for the DD potential or the GND potential is formed.

[0023]

1 is a layout pattern diagram of a semiconductor integrated circuit showing a first embodiment of the present invention.

In FIG. 1, this embodiment uses VDD, G
The layout of basic cells and wiring of signal lines other than ND wiring are shown in FIG.
Since it is the same as the conventional example, detailed description thereof will be omitted.

The VDD and GND wirings are VDs in all areas where the minimum wiring interval portion around the signal wirings in the area where the signal wirings 5 of the third wiring layer do not pass over the basic cell 10.
The wirings for D and GND are used, and the VDD and GND wirings are VDD, GND wirings 3 and 4 of the second wiring layer in the basic cell 10.
And through hole 9 for connection.

FIG. 2 is a layout pattern diagram showing the third wiring layers 6, 7 and the like of FIG.

In FIG. 2, such VDD, GND
To create the wiring pattern, first, VDD, G of the third wiring layer
Layout patterns other than ND are designed by the same method as the conventional method, and among the layout patterns created after that,
Only the pattern of the third wiring layer is thickened by a uniform wiring interval by computer processing, inverted data of the data is created, and the inverted data and the layout other than VDD and GND of the third wiring layer created by the conventional method are created. It can be easily created by taking the OR logic of the pattern data.

Referring to FIG. 3 which is a layout pattern diagram of the second embodiment of the present invention, in this embodiment, the portion of the third wiring layer on the basic cell 10 where the signal wiring does not pass is VD.
These are D and GND wirings 6 and 7. The wirings 6 and 7 are connected to the terminals 20 and 21, respectively.

As described above, by utilizing the region between the signal wirings of the third wiring layer as the VDD and GND wirings 6 and 7, the area under the wiring layer as in the conventional example shown in FIGS. It is possible to reduce the wiring area only for the VDD and GND wirings in which no transistor is formed, and it is possible to improve the integration degree of the semiconductor integrated circuit.

Further, in a semiconductor integrated circuit having a dynamic circuit, when wiring a dynamic signal for holding electric charges by the wiring capacitance in the third wiring layer, the inter-wiring capacitance between the wirings of the third layer running in parallel next to each other. The circuit may malfunction due to the influence of the electric charge stored in.

However, according to the semiconductor integrated circuit of the present invention, since the VDD or GND wiring is inserted between the signal wirings, this serves as a shield and the cause of the malfunction can be eliminated.

[0032]

As described above, according to the present invention, between the plurality of signal wirings formed by the third wiring layer, the VD is formed in the vacant region on the transistor through which the third layer wiring can further pass.
By forming the D or GND wiring, it is possible to reduce the wiring area only for the VDD and GND wirings in which no transistor is formed under the wiring layer, improve the integration degree of the semiconductor integrated circuit, and reduce the chip size. It has the effect of being able to.

Further, when the semiconductor integrated circuit has a dynamic circuit, there is an effect that it is possible to eliminate the cause of malfunction of holding and holding due to the capacitance between the wirings of the signal wirings of the third wiring layer.

[Brief description of drawings]

FIG. 1 is a layout pattern diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a layout pattern diagram showing only a third wiring layer of the layout patterns shown in FIG.

FIG. 3 is a layout pattern diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a layout pattern diagram of a basic cell.

FIG. 5 is a layout pattern diagram of a semiconductor integrated circuit showing a conventional example.

6 is a layout pattern diagram showing only a third wiring layer in the layout pattern shown in FIG.

FIG. 7 is a layout pattern diagram of a semiconductor integrated circuit showing a conventional example.

FIG. 8 is a layout pattern diagram of a semiconductor integrated circuit showing another conventional example.

[Explanation of symbols]

1 signal wiring of the first wiring layer 2 signal wiring of the second wiring layer 3,11 VDD wiring of the second wiring layer 4,12 GND wiring of the second wiring layer 5 signal wiring of the third wiring layer 6 of the third wiring layer VDD wiring 7 GND wiring of third wiring layer 8, 15 Contact 9 connecting first wiring layer and second wiring layer 9 Through hole connecting second wiring layer and third wiring layer 10 Basic cell 13 First wiring layer Inverter input signal 14 Inverter input signal of second wiring layer 16 P-type diffusion layer 17 N-type diffusion layer 18 Contact connecting second wiring layer and diffusion layer 19 Inverter output signal of second wiring layer 20 VDD terminal 21 GND terminal

Claims (1)

[Claims] 1. A plurality of transistors provided on a semiconductor chip and at least three first, second, and third wiring layers insulated from each other by an interlayer insulating film are provided.
In the semiconductor integrated circuit in which the gate of the transistor is formed by the wiring layer and the plurality of transistors are connected by the first, second, and third wiring layers, the second and third wiring layers are oriented in directions orthogonal to each other. And a wiring for a power supply potential or a ground potential is formed in a vacant region on the passable transistor of the third wiring layer between the plurality of wirings formed by the third wiring layer. A semiconductor integrated circuit characterized by the above.