JPH02238661A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid a signal delay in a word line of a masked ROM and to enhance a yield of chips when a large-capacity and high-speed masked ROM is manufactured by a method wherein a redundant memory cell composed of a one-layer gate type EPROM is provided. CONSTITUTION:A control gate is constituted of an impurity region 3 formed by diffusing impurities to a silicon substrate 1. A write voltage which has been applied to an electrode 6 is divided into a floating gate 5 by a gate oxide film 4. As a result, carriers flowing between a source and a drain are injected into the floating gate, stored and written. Accordingly, a polycide can be used for the floating gate 5; since a lower layer constituting the polycide is polysilicon, an insulating layer between the control gate 3 and the floating gate 5 does not come into contact with a silicide; there is no danger that a dielectric breakdown strength and a stored-charge retention characteristic are deteriorated. Thereby, a redundant memory cell can be formed without sacrificing an operating speed of a masked ROM; it is not required to increase the number of manufacturing processes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a mask ROM (Read Only Memory) having redundant memory cells.

[Conventional technology]

With the increase in capacity in recent years, the chip yield of mask ROMs has been decreasing. The main cause of this is dust that adheres at a certain probability per unit area of the semiconductor substrate surface during the manufacturing process, but as the capacity of mask ROM increases and the area of each MOS transistor that makes up the memory cell decreases, Alternatively, the larger the chip size, the more likely defective transistors will occur.

Conventionally, a method has been adopted in which a spare memory cell, that is, a redundant memory cell is provided on each semiconductor substrate, and a defective memory cell is functionally replaced by the redundant memory cell. In the case of a mask ROM, since data is already fixed in a memory cell in which a defective memory cell is found after manufacturing, the redundant memory cell that is replaced with the defective memory cell will contain the data that should be fixed in the defective memory cell. must be writable and non-volatile so that this data can be fixed. In other words, as a redundant memory cell, writable RO
M is required. Such redundant storage cells include electrically programmable ROM, or EPROM (
Electrically programmable
ROM) is appropriate.

[Problem to be solved by the invention]

By the way, in a mask ROM, the gate I of the MOS transistor for storing fixed data also serves as a word line. Therefore, in order to reduce signal delay, gates and word lines are constructed using silicide, which has a lower resistance than 1 polysilicon.

On the other hand, a normal EPROM has a two-layer structure including a floating gate 20 and a control gate 21, as shown in FIG. 3, and a polysilicon layer is used as the floating gates 1 and 20. This is to avoid deterioration of the insulation properties of the insulation layer between the floating gate 20 and the control gate 21.

That is, in general, an oxide film formed on silicide has a low dielectric strength voltage and a large leakage current.

Therefore, when polycide is used for the floating gate 20, the insulating layer between the floating gate 20 and the control gate 21 is in contact with the silicide that forms the upper layer of the polycide, so dielectric breakdown is likely to occur during writing. A problem arises in that the accumulated charge of 21 leaks, making it difficult to retain the written data. On the other hand, polysilicon is used for the floating gate 20 because an oxide film formed on polysilicon has good insulating properties.

When a redundant memory cell consisting of an EPROM having a floating gate 20 and a controller/roll gate 21 having a two-layer structure as described above is formed on a mask ROM substrate, the word line of the mask ROM, that is, the fixed data storage M
OS transistor gate and floating gate 20
It is desirable to form the same conductive layer from the second step. However, for the reasons mentioned above, the word line must be formed from a polysilicon layer with relatively high resistance. As the word line width becomes finer as the capacity of the mask ROM increases, the resistance value increases more and more, and as a result, the reading speed of the mask ROM becomes noticeably lower.

SUMMARY OF THE INVENTION An object of the present invention is to enable redundant storage cells to be provided without increasing signal delay in word lines of a mask ROM.

[Means to solve the problem]

The above object includes a semiconductor substrate, a word line formed by patterning a polycide layer formed on the semiconductor substrate via a gate insulating film, a part of the word line as a gate electrode, and an impurity in the semiconductor substrate. 5. A mask ROM having a MOS transistor as a memory cell as a source and drain formed by selectively introducing impurities into the floating gate formed by patterning the polycide layer, and the semiconductor substrate. This is achieved by the semiconductor device of the present invention, which is characterized in that it is equipped with a redundant memory cell consisting of a single-layer gate type EPRO) I, and a source and drain formed as a single layer.

[For production]

In contrast to the EPROM in which the floating gate and control gate have a two-layer structure as shown in FIG. 3, a single-layer EPROM as shown in FIG.
2-076679).

In this structure, an impurity region 3 formed by diffusing impurities into a silicon substrate 1 constitutes a control gate. The write voltage applied to electrode 6 is divided into floating gate 5 by gate oxide film 4 . As a result, carriers flowing between the source/drain (not shown) are injected and accumulated in the floating gate, and writing is performed.

According to the structure shown in FIG. 4, polycide can be used for the floating gate 5. In other words, since the lower layer constituting the polycide is polysilicon, the insulating layer between the control gate 3 and the floating gate 5 does not come into contact with the silicide, resulting in the deterioration of the dielectric strength voltage and stored charge retention characteristics as described above. There's no fear.

Therefore, the fourth cell is used as a redundant memory cell of the mask ROM.
If an EPROM having a single-layer gate structure as shown in the figure is used, both the gate of the fixed data storage MOS transistor, that is, the word line, and the floating gate of the redundant storage cell EPROM can be formed of polycide. As a result, redundant memory cells can be provided without sacrificing the operating speed of the mask ROM, and there is no need to increase the number of steps.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 respectively show the mask RO of the present invention.
Single-layer gate type EPRO for redundant storage cells configuring M
FIG. 3 is a schematic configuration diagram of M and a fixed data storage cell section.

In Figure 1, (a) and (b) are respectively. Main part? In these figures, an n-type impurity region 3, for example, is formed in a predetermined region A of a p-type silicon substrate 1 separated by an isolation insulating layer 2. Silicon substrate 1
A gate oxide film 4 made of SiO2 and having a thickness of 200 to 300 nm and a floating gate 5 in contact with the gate oxide film 4 are formed on the surface.

Impurity region 3 functions as a control gate, and when a write voltage is applied through electrode 6, this write voltage is divided to floating gate 5. As a result, the n-type source and drain 10 formed in region B
Electrons flowing through the channel region 11 between the two are accelerated and injected into the floating gate 5. Writing is performed in this manner.

In addition, in the same figure, the code 7 is . For example, interlayer insulating layers 7, 12 and 1 made of PSG (phosphosilicate glass)
3 are a source/drain contact and a control gate contact, respectively.

Floating gate 5 has conventionally been composed of a single polysilicon layer, but in the present invention, a lower layer 5^ of approximately 2000 nm thick made of polysilicon and a lower layer 5^ made of, for example, tungsten silicide (WSiz) is used. Approximately 20
It is composed of a so-called polycide layer having a two-layer structure with an upper layer 5B.

On the other hand, in FIG. 2(a), source and drain regions 8 formed by implanting n-type impurities, for example, are formed in the same silicon substrate 1 as described above. A word line 9 is formed on the surface of the silicon substrate 1 between each source and drain region 8 and is in contact with the silicon substrate 1 via the same gate oxide film 4 as described above. Word line 9 extends perpendicularly to the plane of the paper and runs between other source and drain regions (not shown) that are equivalent to source and drain region 8 .

One MOS transistor is constituted by a pair of source and drain regions 8 and a word line 9.

Therefore, source and drain regions 8 as shown
A MOS transistor T whose source and drain are connected in series as shown in FIG.
r columns are constructed. Both ends of the MOS transistor string are connected to a bit line BL (not shown) and a power supply line, such as Vss.
are connected to each. A mask ROM is constructed by arranging a plurality of such MOS transistors Tr arrays in parallel.

In the above mask ROM, the word line 9 also has a lower i9A made of a polycide layer, that is, polysilicon. For example, it is composed of an upper layer 9B made of klsi2.

The lower layer 9A and the upper layer 9B are formed by patterning the same polysilicon layer and -Siz layer as the lower layer 58 and the upper layer 5B in FIG. 1(a), respectively.

The polysilicon layer constituting the lower layers 5A and 9A and the -Si2 layer constituting the upper layers 5B and 9B in the above are both deposited on the silicon substrate 1 using the well-known CvD method. Note that, like a normal mask ROM, the mask ROM shown in FIG. 2 also has a MOS for fixed data storage.
All of the transistors Tr are manufactured to be of the enhancement type, and only the MOS transistors Tr to which fixed data is not written are converted to the depletion type. Thereafter, a polycide layer constituting the floating gate 5 and word line 9 is formed.

The polycide layer is patterned into floating gates 5 and word lines 9. This patterning can be performed by the well-known RIE (reactive ion etching). For example, using a resist mask and using a fluorine-based or chlorine-based gas as an etching agent,
B and the lower layers 58 and 9A are successively etched.

Thereafter, an interlayer insulating layer 7 made of, for example, PSG is formed on the silicon substrate 1, and contact holes are formed in predetermined regions of the interlayer insulating layer 70. For example, a thin aluminum film is deposited on the interlayer insulating layer 7 and patterned to form the electrode 6 connected to the impurity region 3, thereby completing the mask ROM of the present invention.

〔Effect of the invention〕

According to the present invention, it is possible to avoid the signal delay in the word line of the mask ROM caused by the provision of redundant memory cells, and it is possible to improve the chip yield in manufacturing a large-capacity, high-speed mask ROM. be.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a redundant storage cell in the present invention. FIG. 2 is a schematic block diagram of a fixed data storage cell section in the present invention. FIGS. 3 and 4 are conventional EPI? It is a sectional view of the main part of OM. In the figure, 1 is a silicon substrate 2 is an isolation insulating layer, 3 is an impurity region 4 is a gate oxide film, 5 and 20 are floating gates 5A and 98 are lower layers, 5B and 9B are upper layers 6 is an electrode, 7 is an insulating layer between the eyebrows , 8 are source and drain regions. 9 is a word line, 10 is a source and drain, 11 is a channel region, 12 is a source/drain contact, 13 is a control gate contact, and 21 is a control gate.

Claims (1)

[Scope of Claims] A semiconductor substrate, a word line formed by patterning a polycide layer formed on the semiconductor substrate via a gate insulating film, a part of the word line serving as a gate electrode, and the semiconductor substrate A mask ROM having as a memory cell a MOS transistor formed by selectively introducing impurities into a semiconductor substrate, a floating gate formed by patterning the polycide layer, and a semiconductor substrate having impurities selectively introduced into the semiconductor substrate. 1. A semiconductor device comprising: a redundant memory cell comprising a single-layer gate type EPROM comprising a source and a drain formed by introducing the semiconductor device into the semiconductor device.