JPH02238678A - Photo-detector - Google Patents
Photo-detectorInfo
- Publication number
- JPH02238678A JPH02238678A JP1057977A JP5797789A JPH02238678A JP H02238678 A JPH02238678 A JP H02238678A JP 1057977 A JP1057977 A JP 1057977A JP 5797789 A JP5797789 A JP 5797789A JP H02238678 A JPH02238678 A JP H02238678A
- Authority
- JP
- Japan
- Prior art keywords
- inductance
- light receiving
- circuit
- delta
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Light Receiving Elements (AREA)
- Optical Communication System (AREA)
Abstract
Description
【発明の詳細な説明】 「発明の目的」 （産業上の利用分野） 本発明は、得に高速応答性を有する受光素子に関する。[Detailed description of the invention] "Purpose of invention" (Industrial application field) The present invention particularly relates to a light-receiving element having high-speed response.
（従来の技術）
高速光通信技術において、ＰＩＮフォ１〜ダイＡ−ドを
始めとする高速受光素子の重要性がまずまず高まってい
ることから、受光素子単体の高速速化は当然ながら、素
子のもつ特性を最大に引ぎ出せるような回路構成が強く
望まれている。(Prior art) In high-speed optical communication technology, the importance of high-speed light-receiving elements such as PIN photodiodes to diode is increasing, so it goes without saying that the speed of a single light-receiving element must be increased. There is a strong desire for a circuit configuration that can bring out the maximum characteristics.
第２図（ａ），（ｂ）は従来の受光素子の信号取り出し
まで含めた構成例を示すしので、（ａ）は外観構成図、
（ｂ）は等価回路図である。第２図（ａ＞において、２
１は受光素子ヂップ２２の受光面であり、電気信号は取
り出し電極パッド２３を介し、ワイヤーボンド２４によ
り外部のス１〜リップ線路２５へ導出されている。FIGS. 2(a) and 2(b) show an example of the configuration of a conventional light-receiving element including signal extraction, so (a) is an external configuration diagram;
(b) is an equivalent circuit diagram. In Figure 2 (a>, 2
Reference numeral 1 denotes a light receiving surface of a light receiving element dip 22, and an electric signal is led out to an external slip line 25 through a wire bond 24 via an extraction electrode pad 23.
第２図（ｂ）において、ＩＰは電気信号の電流源であり
、ＲＳは受光素子２２内部のシリーズ抵抗である。ＣＪ
は接合の内部容揚であり、ＬＢはワイヤボンド２４の接
続インダクタンス、ＴＲは伝送線路を表し、ＲＬは外部
終端抵抗である。第２図（ｂ）において破線で示す部分
が受光素子チップ２２′Ｃ：あり、主に容ｆｆｉ Ｃ
Ｊが素子の周波数帯域を規定する。In FIG. 2(b), IP is a current source of an electric signal, and RS is a series resistance inside the light receiving element 22. C.J.
is the internal capacitance of the junction, LB is the connection inductance of the wire bond 24, TR represents the transmission line, and RL is the external termination resistance. In FIG. 2(b), the part indicated by the broken line is the light receiving element chip 22'C: which mainly contains
J defines the frequency band of the element.
（発明が解決しようとする課題）
ところで、実際の素子特性は接続インダクタンスや浮遊
容量など実装構造により強く制限を受ける。ワイＶ−ボ
ンド２４の場合、接続インダクタンスＬ ［３の値は通
常およそ１ｎＨ弱程度であり、接続構造をフリップ・チ
ップ構造にした場合には、接続インダクタンスＬＢの値
は、数十ｐ｝−１に小さくできる。しかし、いずれの構
造にしても、これらの外部付加要素による広帯域化は、
従来、接合容ｆｍ Ｃ Ｊと接続インダクタンスＬ−
Ｂの単純な共振効果のみを利用した範囲に限定される。(Problems to be Solved by the Invention) However, actual device characteristics are strongly limited by the mounting structure such as connection inductance and stray capacitance. In the case of the W-V-bond 24, the value of the connection inductance L [3 is normally about a little less than 1 nH, and when the connection structure is a flip chip structure, the value of the connection inductance LB is several tens of p}-1 It can be made smaller. However, in either structure, widening the bandwidth by using these external additional elements is
Conventionally, junction capacitance fm C J and connection inductance L-
It is limited to the range that utilizes only the simple resonance effect of B.
このため、Ｊ；り広帯域化を図るための有効な対策が切
望されていた。For this reason, there has been a strong need for effective measures to increase the bandwidth.
本発明は上記に鑑みてなされたもので、その目的として
は、広い周波数帯域を有する受光素子を提供することに
ある。The present invention has been made in view of the above, and an object thereof is to provide a light receiving element having a wide frequency band.
［発明の構成］
（課題を解決するための手段）
」二記目的を達成するため、本発明は、受光部から受光
吊に応じて出力される電気信号の一部を分岐づ−る分岐
回路と、この分岐回路における分岐出力と接地との間に
接続されたインダクタンスとを有ずることを要旨とする
。[Structure of the Invention] (Means for Solving the Problems) In order to achieve the second object, the present invention provides a branch circuit that branches a part of the electrical signal output from the light receiving section in accordance with the light receiving level. and an inductance connected between the branch output and ground in this branch circuit.
〈作用）
本発明に係る受光素子にあっては、受光部からの受光量
に応じた電気信号の一部を例えばデルタ形抵抗回路ある
いはＹ形抵抗回路で構成ざれる分岐回路で分岐して接地
されているインダクタンスに供給づ−ることで、分岐ざ
れない出力側に接続される外部負荷に対し最適なビーキ
ング特性をイ」加している。<Function> In the light-receiving element according to the present invention, a part of the electric signal corresponding to the amount of light received from the light-receiving section is branched to a branch circuit composed of a delta-type resistance circuit or a Y-type resistance circuit and grounded. By supplying the inductance to the inductance, the optimum beaking characteristic is added to the external load connected to the unbranched output side.
（実施例） 以下、図面を用いて木発明の実施例を説明する。(Example) Embodiments of the wooden invention will be described below with reference to the drawings.
第１図（ａ），（ｂ）は本発明の−実施例をホすもので
、第１図（ ａ ）は受光素子チツブ１の構成外観図、
第１図（ｂ）はその等価回路図である。FIGS. 1(a) and 1(b) show an embodiment of the present invention, and FIG. 1(a) is an external view of the configuration of a light receiving element chip 1;
FIG. 1(b) is an equivalent circuit diagram thereof.
その特徴としては、受光面２１から電極パッド２３に至
る経路途中に薄膜抵抗４，５．６から椙成されるデルタ
形抵抗回路２を接続すると共に、抵抗５ど抵抗６との接
続点と接地而７との間に薄膜金属からなるシャン１へ・
インダクタンス８を接続して、受光素子ヂップ１の出力
回路として、この＝３
デルタ形抵抗回路２とシャント・インダクタンス８を含
む回路により、固定ざれた外部接続インダクタンスＩＢ
に対応した最適な並列共振によるピーキング効果を設定
できるようにしたことにある。Its features are that a delta resistor circuit 2 formed from thin film resistors 4 and 5.6 is connected in the middle of the path from the light receiving surface 21 to the electrode pad 23, and the connection point between the resistor 5 and the resistor 6 is grounded. Between 7 and 7, there is a thin film of metal between 1 and 1.
By connecting the inductance 8, the output circuit of the photodetector Zip 1 is created using a circuit including the =3 delta type resistor circuit 2 and the shunt inductance 8, and the externally connected inductance IB is fixed.
The aim is to make it possible to set the optimal peaking effect due to parallel resonance corresponding to the
ここで、デルタ形抵抗回路２は、電流源ＩＰからの電流
を電極パツド２３への経路とシャント・インタクタンス
８への経路とに分流τるためのもので、その分流割合と
しては抵抗４，５．６の値による。なｄ３、第１図（ａ
）．（ｂ）において、第２図（ａ），（ｂ）と同一物に
は同−符号を付して、詳細な説明は省略する。Here, the delta type resistor circuit 2 is used to divide the current from the current source IP into a path to the electrode pad 23 and a path to the shunt inductance 8, and the dividing ratio is 4, According to the value of 5.6. d3, Figure 1 (a
). In (b), the same parts as in FIGS. 2(a) and 2(b) are given the same reference numerals, and detailed description thereof will be omitted.
次に、具体的な数値例をあげて本実施例を従来例と比較
する。第２図において、
ＲＳ＝２０Ω，ＲＬ＝５０Ω．ＬＢ＝２０ｐＨくフリッ
プ・チップ実装），ＣＪ＝０．１ｐＦ，ＴＲの特性イン
ピーダンスＺｏ＝５０Ω，遅延時間一「Ｄ ＝ ４ ０
ｐ ｓ ．
等の値を用い、ｌ． Ｂを調節し最適化（ｌＢ＝１０［
） ｌ−１ ） Ｌた場合、帯域幅は１６７ＧＨＺとな
る。Next, this example will be compared with the conventional example using specific numerical examples. In FIG. 2, RS=20Ω, RL=50Ω. LB=20pH (flip chip mounting), CJ=0.1pF, TR characteristic impedance Zo=50Ω, delay time D=40
ps. Using values such as l. Adjust and optimize B (lB=10[
) l-1 ) L, the bandwidth is 167 GHZ.
これに対して、第１図（ａ）において、信号電源振幅も
含め前記の値を採用し、これらの値に対応し、周波数特
性をほぼ最適化した飴として、抵抗４−０．１０，抵抗
５ ＝ ５ ０ ０ ，抵抗６−８０Ω，シャント・イ
ンタクタンス８ ＝ ４ ０ １）Ｈ．
等を採用すると、回路解析シミコレーションにＪ、る３
ｄＢ帯域は１８２Ｇｌ−１ｚとなる。これは、信号源側
からみた負荷インピーダンスがデルタ形抵抗回路２の付
加により低下した効果と、シャン１〜・インダクタンス
８による並列共振効東がイ」加ざれた相乗効果のためで
ある。On the other hand, in Fig. 1(a), the above values including the signal power supply amplitude are adopted, and corresponding to these values, the resistance 4-0.10, the resistance 5 = 5 0 0, resistance 6-80 Ω, shunt inductance 8 = 4 0 1) H. etc., for circuit analysis simulation.
The dB band is 182Gl-1z. This is due to the effect that the load impedance seen from the signal source side is reduced by the addition of the delta resistor circuit 2, and the synergistic effect that the parallel resonance effect due to the inductances 1 to 8 is added.
なお、ここで、０．１Ωという飴の抵抗４については、
製作が難しいがその許容範囲は広く、ＯＯ１Ω〜０．２
Ω変動し゛（も帯域は１８０〜１８２ＧＨｚ Ｌか変化
しないので、然程の困難性とはならない。In addition, here, regarding the candy resistance 4 of 0.1Ω,
It is difficult to manufacture, but the tolerance range is wide, OO1Ω~0.2
Ω fluctuates (but the band does not change from 180 to 182 GHz L, so it is not very difficult.
したがって、本実施例によれば、従来に比へて広帯域化
を図ることができる。また、抵抗や、インダクタンス要
素を微細な薄膜で受光素子チップ内に形成するようにし
ているので、浮遊な要素が｛＝Ｊ加しにくく設計が容易
となり、製作にｄ３いても受光素子中体の製作と共通化
できる。Therefore, according to this embodiment, it is possible to achieve a wider band than in the past. In addition, since the resistor and inductance elements are formed with fine thin films inside the photodetector chip, it is difficult for floating elements to be added to the photodetector chip, making the design easier. Can be shared with production.
なｄ３、本実施例では、シャント・インダクタンス８へ
の分流をデルタ形抵抗回路２を用いたが、これと等価な
Ｙ形抵抗回路でもよく、所要抵抗値の製作容易性に基づ
いてずれを選択すればよい。d3. In this example, the delta-type resistor circuit 2 is used to divert the current to the shunt inductance 8, but a Y-type resistor circuit equivalent to this may also be used, and the deviation can be selected based on the required resistance value and ease of manufacture. do it.
［発明の効果１
以上説明したように本発明によれば、受光部からの受光
最に応じた電気信号の一部を例えばデルタ形抵抗回路あ
るいはＹ形抵抗回路で構成ざれる分岐回路で分岐して接
地されているインダクタンスに供給ザることで、分岐さ
れない出力側に接続される負荷に対し最適なビーギング
特性をイ」力日しているので、広い周波数帯域を有する
受光素子を提供することができる。[Effect of the Invention 1] As explained above, according to the present invention, a part of the electric signal depending on the amount of light received from the light receiving section is branched by a branch circuit composed of, for example, a delta-type resistance circuit or a Y-type resistance circuit. By supplying the inductance to the grounded inductance, the optimal beaging characteristic is achieved for the load connected to the unbranched output side, making it possible to provide a light receiving element with a wide frequency band. can.
第１図（ａ）は本発明の一実施例を示す図であり、第１
図（ｂ）は当該一実施例の等価回路を示す図、第２図（
ａ）は従来の構成図であり、第２図（ｂ）はその等価回
路を示す図である。
１・・・受光素子チップ
２・・・デルタ形抵抗回路
４，５．６・・・薄膜抵抗
７・・・接地面
８・・・シャント・インダクタンス
２１・・・受光面
２２・・・受光素子チップ
２３・・・電極パッド
２４・・・ワイヤーボンド
２５・・・ストリップ線路
８３・・・■Ｐ；電流源
８５・・・ＲＳ：シリーズ抵抗
８７・・・ＣＪ：接合容量
８９・・・ＬＢ：接続インダクタンス
９１・・・ＴＲ：伝送線路
９３・・・ＲＬ：外部終端抵抗FIG. 1(a) is a diagram showing one embodiment of the present invention.
Figure (b) is a diagram showing the equivalent circuit of this example, and Figure 2 (
2(a) is a conventional configuration diagram, and FIG. 2(b) is a diagram showing its equivalent circuit. 1... Light-receiving element chip 2... Delta-type resistance circuit 4, 5.6... Thin-film resistor 7... Ground plane 8... Shunt inductance 21... Light-receiving surface 22... Light-receiving element Chip 23...Electrode pad 24...Wire bond 25...Strip line 83...P; Current source 85...RS: Series resistance 87...CJ: Junction capacitance 89...LB: Connection inductance 91...TR: Transmission line 93...RL: External terminating resistance
Claims (2)
一部を分岐する分岐回路と、この分岐回路における分岐
出力と接地との間に接続されたインダクタンスとを有す
ることを特徴とする受光素子。(1) It is characterized by having a branch circuit that branches part of the electrical signal output from the light receiving section according to the amount of light received, and an inductance connected between the branch output of this branch circuit and ground. Light receiving element.
抗回路であることを特徴とする請求項１記載の受光素子
。(2) The light receiving element according to claim 1, wherein the branch circuit is a delta type resistance circuit or a Y type resistance circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1057977A JP2952302B2 (en) | 1989-03-13 | 1989-03-13 | Light receiving element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1057977A JP2952302B2 (en) | 1989-03-13 | 1989-03-13 | Light receiving element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02238678A true JPH02238678A (en) | 1990-09-20 |
| JP2952302B2 JP2952302B2 (en) | 1999-09-27 |
Family
ID=13071064
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1057977A Expired - Fee Related JP2952302B2 (en) | 1989-03-13 | 1989-03-13 | Light receiving element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2952302B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2713194A2 (en) | 2012-08-31 | 2014-04-02 | Fujitsu Limited | Optical module |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52116002A (en) * | 1976-03-25 | 1977-09-29 | Fujitsu Ltd | Photo receiving circuit |
| JPS5434791A (en) * | 1977-08-24 | 1979-03-14 | Mitsubishi Electric Corp | Receiver for photo signal |
| JPS562673A (en) * | 1979-06-22 | 1981-01-12 | Hitachi Cable Ltd | Optical receiver circuit |
| JPS6224667A (en) * | 1985-07-24 | 1987-02-02 | Fujitsu Ltd | Photoelectronic integrated circuit element |
-
1989
- 1989-03-13 JP JP1057977A patent/JP2952302B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52116002A (en) * | 1976-03-25 | 1977-09-29 | Fujitsu Ltd | Photo receiving circuit |
| JPS5434791A (en) * | 1977-08-24 | 1979-03-14 | Mitsubishi Electric Corp | Receiver for photo signal |
| JPS562673A (en) * | 1979-06-22 | 1981-01-12 | Hitachi Cable Ltd | Optical receiver circuit |
| JPS6224667A (en) * | 1985-07-24 | 1987-02-02 | Fujitsu Ltd | Photoelectronic integrated circuit element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2713194A2 (en) | 2012-08-31 | 2014-04-02 | Fujitsu Limited | Optical module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2952302B2 (en) | 1999-09-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |