JPH02239721A - Output interface circuit - Google Patents

Abstract

PURPOSE:To surely keep an output signal level to a high level even at the time of rising a power voltage by inserting a 1st resistor between an output terminal of an emitter follower AND gate and a 2nd resistor whose one terminal connects to a base of a transistor(TR) and whose other terminal connects to ground. CONSTITUTION:A power-on reset circuit 1 is not normally operated when a power voltage Vcc is in a range of 0-1.4V at the time of rising and not kept to an output low level, then an output voltage level Vout of an emitter follower AND gate 2 does not keep a low level and a TR 5 is going to be operated. However, with Vcc=0-1.4V, a maximum output voltage of the emitter follower AND gate 2 is selected as Voutmax<=1.4V, a voltage across a 2nd resistor 4 having a resistor r2 is lower than a minimum operating voltage VBEONmin of the TR 5 with a 1st resistor 3 having a resistance rl obtained from equation I, the TR 5 is not operated and a high output signal level is surely warranted even at the time of rising the power voltage Vcc.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an output interface circuit that ensures that an interface signal remains at the old GH level even when a power supply Vcc rises.

2. Description of the Related Art Conventionally, as shown in FIG. 2, this type of output interface circuit includes an emitter follower type AND gate 2 having a power-on reset circuit 1 connected to one of its input terminals, and an emitter follower type AND gate 2 connected to the power-on reset circuit 1 at one of its input terminals. A resistor 4 with one end connected to the output terminal and the other end connected to the ground, a transistor 5 whose base terminal is connected to the output terminal of the emitter follower type AND gate 2, an emitter terminal connected to the ground, and one end connected to the collector terminal of the transistor 5. , the other end is connected to the power supply voltage Vcc supply terminal l3.
(up) resistor 8 and an output pin 7 connected to the collector terminal of the transistor 5.

As for the operation of the circuit, when the power supply voltage Vcc rises, the power-on reset circuit 1 operates until the voltage Vcc is determined, and the input terminal of the emitter follower type AND gate 2 is set to Lo.
Since the output terminal is at the t level, the output terminal is also at the low level, and since the transistor 5 does not operate, the output pin 7 maintains the old gh level.

Problems to be Solved by the Invention The conventional interface circuit described above has a power supply [voltage Vc
The power-on reset circuit 1 is designed to maintain the low level at the rise of the power supply voltage Vcc, but in reality, the power-on reset circuit 1 maintains the low level at the rise of the power supply voltage Vcc.
．． When in the 4V range: ζLow level cannot be guaranteed, and as the voltage Vcc rises, the output level of the power-on reset circuit 1 also rises, and therefore the output level V out of the emitter follower type AND gate 2 also rises. The maximum value V out+*ax is the transistor 5
If the lowest operating voltage V BEONmIn is exceeded, the transistor 5 will operate, and the output of the interface circuit will not be able to guarantee the old GH level and will go to Low level, causing other interface circuits to operate. there were.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel output interface circuit that makes it possible to solve the above-mentioned problems inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, an output interface circuit according to the present invention has one end connected to an output terminal of an emitter follower type AND gate and a base terminal of a transistor,
It is configured to include a first resistor inserted between a second resistor and a second resistor whose other end is connected to ground.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Referring to FIG. 1, one embodiment of the present invention includes a power-on reset circuit 1 and an emitter follower type AND gate 2.
, a first resistor 3, a second resistor 4, a transistor 5 that inverts the output of the emitter follower type AND gate 2, a resistor 6 that pulls up the collector terminal of the transistor 5, and an output pin 7. configured.

Next, to explain the operation of the present invention, the power supply voltage Vcc
Within the range of 0 to 1.4 V when V out rises, the power-on reset circuit 1 does not operate normally and cannot maintain the output at Lot level. cannot maintain the low level, and the transistor 5 tries to operate. However, when Vcc=O~1.4 V, the maximum output voltage of the emitter follower type AND gate 2 is V outmax≦1
．． 4 V1 The resistance value of the first resistor 3 is r1, the second resistor 4
The resistance value of is r2, and the minimum operating voltage of the transistor is VBE.
As ONmIn, the resistance value rl obtained from the relational expression
Since the voltage across the second resistor 4 becomes lower than VBEONmin due to the first resistor 3 having a voltage of Signal level Hi
gh level can be guaranteed.

Effects of the Invention As explained above, according to the present invention, one end of the second resistor 4 is connected to the output terminal of the emitter follower type AND gate 2, one end of which is connected to the base terminal of the transistor 5, and the other end is connected to the ground. By inserting a first resistor 3 having a resistance value rl determined by the formula between
When the voltage rises, the output voltage level of the emitter follower type AND gate 2 becomes L when it is within the range of 0 to 1.4 V.
Even if the OW level cannot be maintained and increases, the voltage across the second resistor 4 will drop below the transistor's minimum operating voltage VBEON+sin due to the voltage drop caused by the first resistor 3, and as a result, the transistor 5 will never operate. , it is possible to reliably maintain the output signal level of the interface at the old gh level.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional example. 1. ．． ．． Power-on reset circuit, 2. ．． ．． Emitter follower type AND gate, 3, 4. ．． ．． Resistance, 5. ．． transistor, 6. 、． Pull up resistor, 7. ．． ．． Output bin, l! , l2, 13. ．． ．． Voltage Vcc supply terminal

Claims (1)

[Claims] an emitter follower type AND gate having a power-on reset circuit connected to one of its input terminals; a first resistor having one end connected to the output terminal of the emitter follower type AND gate; and one end connected to the other end of the first resistor. a second resistor whose base terminal is connected to the other end of the first resistor and whose emitter is connected to the ground; and a transistor whose one end is connected to the collector terminal of the transistor and whose other end is connected to the ground. An output interface circuit comprising: a pull-up resistor whose end is connected to a power supply; and an output pin connected to a collector terminal of the transistor.