JPH0224015B2 - - Google Patents
Info
- Publication number
- JPH0224015B2 JPH0224015B2 JP55156540A JP15654080A JPH0224015B2 JP H0224015 B2 JPH0224015 B2 JP H0224015B2 JP 55156540 A JP55156540 A JP 55156540A JP 15654080 A JP15654080 A JP 15654080A JP H0224015 B2 JPH0224015 B2 JP H0224015B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal wiring
- etching
- forming
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法に係り、特に
配線のパターニングを精度良く行なうことができ
る製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device that can pattern wiring with high precision.
最近のLSI技術では、配線の幅を高密度化のた
めに1.5μ〜2.0μ程度にするという精度の高いパタ
ーニングが要求されている。第１図の各断面図に
て、従来の配線のパターニングを説明する。 Recent LSI technology requires highly precise patterning to reduce the wiring width to approximately 1.5μ to 2.0μ in order to increase density. Conventional wiring patterning will be explained with reference to each cross-sectional view in FIG.
１は、半導体基板で、その上に形成された絶縁
膜２の上にAlやAl合金等の金属配線膜３が形成
され、さらにその上にレジスト膜４が形成されて
いる。レジスト膜４はすでに、露光、現象等によ
りパターニングされている。そして、このレジス
ト膜４をマスクにして金属配線膜３がパターニン
グされる。このパターニングには、エツチング液
中に浸漬するウエツトエツチング（第１図ｂ）
と、エツチングガス囲気中にて行なうドライエツ
チング（第１図ｃ）とがあるが、いずれの場合
も、従来の方法では良好なパターニングは不可能
である。 Reference numeral 1 denotes a semiconductor substrate, on which an insulating film 2 is formed, a metal wiring film 3 made of Al, Al alloy, etc. is formed, and a resist film 4 is further formed thereon. The resist film 4 has already been patterned by exposure, phenomena, etc. Then, the metal wiring film 3 is patterned using this resist film 4 as a mask. This patterning involves wet etching (Fig. 1b), in which the etching is immersed in an etching solution.
and dry etching (FIG. 1c) performed in an etching gas atmosphere, but in either case, good patterning is impossible with conventional methods.
まず第１図ｂのウエツトエツチングの場合、レ
ジスト膜４として通常、ネガレジスト（東京応化
製OMR等）が使用され、エツチング液としてリ
ン酸に僅かの硝酸を加えた混合液が使用される
が、そのエツチング方向は等方的であり、さらに
レジスト膜４と金属配線膜３との密着性が悪く、
その界面にまでエツチング液が浸透するため、サ
イドエツチングが非常に大となり、図中５の如
く、エツチングの精度が悪いものとなる。そこで
密着性を良くするために、レジスト膜４のベーキ
ング温度や時間を大にすると、低融点金属である
Al等よりなる金属配線膜３に高温処理によるア
イグレーシヨンが発生し、エツチング後のパター
ンに切欠き部（いわゆる、虫くいやスプーンカツ
トと称されるもの）が生じてしまう。 First, in the case of wet etching as shown in Fig. 1b, a negative resist (OMR manufactured by Tokyo Ohka Co., Ltd., etc.) is usually used as the resist film 4, and a mixture of phosphoric acid and a small amount of nitric acid is used as the etching solution. , the etching direction is isotropic, and the adhesion between the resist film 4 and the metal wiring film 3 is poor.
Since the etching solution penetrates into the interface, side etching becomes very large, resulting in poor etching accuracy as shown in 5 in the figure. Therefore, in order to improve the adhesion, if the baking temperature and time of the resist film 4 are increased, it is possible to increase the baking temperature and time of the resist film 4.
Eye grating occurs in the metal wiring film 3 made of Al or the like due to high temperature treatment, resulting in cutouts (so-called insect holes or spoon cuts) in the pattern after etching.
また第１図ｃのドライエツチング、特に平行平
板型のドライエツチングの場合、エツチングガス
として、BCl3とPCl3とAr等の混合ガスが、また
レジスト膜としてポジレジスト（東京応化社製
OFPR、シツプレイ社製AZ−1350等）が使用さ
れる。この様なドライエツチングは異方性エツチ
ングであるため、前述した様なウエツトエツチン
グの如きサイドエツチングは生じないが、図中６
の如き横穴が生じたり、又７の如きAlの突起が
生じたりする。前者の横穴については原因は不明
であり、後者については金属配線膜３とレジスト
膜４との密着性が悪いため生じるものと思われ
る。この様な横穴や突起を有する金属配線パター
ンは、実際上良質のパターンとはいえない。 In addition, in the case of the dry etching shown in Fig. 1c, especially the parallel plate type dry etching, a mixed gas such as BCl 3 , PCl 3 and Ar is used as the etching gas, and a positive resist (manufactured by Tokyo Ohka Co., Ltd.) is used as the resist film.
OFPR, Situprey AZ-1350, etc.) are used. Since this type of dry etching is anisotropic etching, side etching like the wet etching described above does not occur, but
Horizontal holes such as the one shown in Fig. 7 are formed, and Al protrusions such as those shown in Fig. 7 are formed. The cause of the former side hole is unknown, and the latter is thought to be caused by poor adhesion between the metal wiring film 3 and the resist film 4. A metal wiring pattern having such side holes or protrusions cannot actually be said to be a high quality pattern.
本発明は、上記従来の欠点をなくすことを目的
とし、その特徴は基板上に形成された絶縁膜上に
Al又はAlを含有する合金からなる金属配線膜を
形成する工程、該金属配線膜の表面にリンシリケ
ートガラス膜又はプラズマCVD法による窒化硅
素膜を形成する工程、該リンシリケートガラス膜
又は窒化硅素膜上にレジスト膜を形成する工程、
該レジスト膜を露光、現像する工程、該レジスト
膜をマスクに該リンシリケートガラス膜又は窒化
硅素膜、及び該金属配線膜をエツチングしてパタ
ーニングする工程を有する半導体装置の製造方法
にある。 The present invention aims to eliminate the above-mentioned conventional drawbacks, and its feature is that the insulating film formed on the substrate is
a step of forming a metal wiring film made of Al or an alloy containing Al; a step of forming a phosphosilicate glass film or a silicon nitride film by plasma CVD on the surface of the metal wiring film; a step of forming the phosphosilicate glass film or silicon nitride film; a step of forming a resist film on top;
The method of manufacturing a semiconductor device includes the steps of exposing and developing the resist film, and etching and patterning the phosphosilicate glass film or silicon nitride film and the metal wiring film using the resist film as a mask.
以下本発明の一実施例を図面に従つて詳細に説
明する。 An embodiment of the present invention will be described in detail below with reference to the drawings.
第２図は本実施例に係る各工程断面図で、それ
ぞれ第１図の従来例に対応している。本実施例で
は、AlやAl含有合金等の金属配線膜３の表面に
厚さ100〜200Å程度の薄い被膜８が形成されてい
る。この被膜８は、リンシリケートガラス膜、プ
ラズマCVD法によるSi3N4膜等レジスト膜４との
密着の良いものが良い。 FIG. 2 is a sectional view of each process according to this embodiment, and each corresponds to the conventional example shown in FIG. 1. In this embodiment, a thin film 8 having a thickness of about 100 to 200 Å is formed on the surface of a metal wiring film 3 made of Al or an Al-containing alloy. This film 8 is preferably one that has good adhesion to the resist film 4, such as a phosphosilicate glass film or a Si 3 N 4 film formed by plasma CVD.
いずれの被膜８にしろ、本発明者の実験によれ
ば、金属配線膜３の表面にレジスト膜４と密着性
の良い被膜８を形成すると、次の様なパターニン
グの効果が得られた。第１の密着性が良いため、
レジスト膜４のポストベーキングは低温かつ短時
間で行なつても良く、ウエツトエツチング（第２
図ｂ）においては、サイドエツチングが少なく、
マイグレーシヨンによる切欠部も生じない。ま
た、ドライエツチング（第２図ｃ）においては、
Alの突起等も生じない。第２のドライエツチン
グ（第２図ｃ）において、従来問題となつていた
パターン側面への横穴も生じないで、良質のパタ
ーンニングが可能である。また、第３の金属配線
膜３の表面が酸化膜等で保護されているため、通
常その上に形成されるリンシリケートガラス膜の
リンと外部からの水分とのリン酸による腐食作用
の防止も可能である。 Regardless of which film 8 is used, according to experiments conducted by the present inventor, when a film 8 having good adhesion to the resist film 4 is formed on the surface of the metal wiring film 3, the following patterning effect can be obtained. Because the first adhesion is good,
Post-baking of the resist film 4 may be performed at a low temperature for a short time, and wet etching (second
In figure b), there is less side etching,
No notches are created due to migration. In addition, in dry etching (Fig. 2c),
No Al protrusions occur. In the second dry etching (FIG. 2c), high-quality patterning is possible without creating horizontal holes on the side surfaces of the pattern, which has been a problem in the past. In addition, since the surface of the third metal wiring film 3 is protected by an oxide film or the like, it is also possible to prevent the corrosion of the phosphorus silicate glass film usually formed thereon by phosphoric acid and moisture from the outside. It is possible.
以上説明した様に本発明によれば、精度の良
い、質の良い金属配線膜のパターニングが可能
で、本発明は、起LSI等の微細加工において非常
に有効なものである。 As explained above, according to the present invention, it is possible to pattern a metal wiring film with high precision and high quality, and the present invention is very effective in microfabrication of integrated LSIs and the like.
第１図は従来例を説明するための断面図、第２
図は本発明の一実施例を説明するための断面図で
ある。
図中、１；基板、２；絶縁膜、３；金属配線
膜、４；レジスト膜、８；被膜。
Figure 1 is a sectional view for explaining the conventional example, Figure 2 is a sectional view for explaining the conventional example;
The figure is a sectional view for explaining one embodiment of the present invention. In the figure, 1: substrate, 2: insulating film, 3: metal wiring film, 4: resist film, 8: film.
Claims (1)
含有する合金からなる金属配線膜を形成する工
程、 該金属配線膜の表面にリンシリケートガラス膜
又はプラズマDVC法による窒化硅素膜を形成す
る工程、 該リンシリケートガラス膜又は窒化硅素膜上に
レジスト膜を形成する工程、 該レジスト膜を露光、現像する工程、 該レジスト膜をマスクに該リンシリケートガラ
ス膜又は窒化硅素膜、及び該金属配線膜をエツチ
ングしてパターニングする工程を有することを特
徴とする半導体装置の製造方法。[Claims] 1. A step of forming a metal wiring film made of Al or an alloy containing Al on an insulating film formed on a substrate, a step of forming a metal wiring film made of Al or an alloy containing Al on the surface of the metal wiring film using a phosphosilicate glass film or a plasma DVC method. a step of forming a silicon nitride film, a step of forming a resist film on the phosphosilicate glass film or the silicon nitride film, a step of exposing and developing the resist film, and a step of forming the phosphosilicate glass film or silicon nitride using the resist film as a mask. A method for manufacturing a semiconductor device, comprising a step of etching and patterning a film and a metal wiring film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55156540A JPS5780723A (en) | 1980-11-07 | 1980-11-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55156540A JPS5780723A (en) | 1980-11-07 | 1980-11-07 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5780723A JPS5780723A (en) | 1982-05-20 |
| JPH0224015B2 true JPH0224015B2 (en) | 1990-05-28 |
Family
ID=15630021
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55156540A Granted JPS5780723A (en) | 1980-11-07 | 1980-11-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5780723A (en) |
-
1980
- 1980-11-07 JP JP55156540A patent/JPS5780723A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5780723A (en) | 1982-05-20 |
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