JPH02241114A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To obtain an output buffer circuit being evaded the flow of a through- current to an output buffer by controlling 1st and 2nd transistors(TRs) in the output buffer so as not to turn on simultaneously based on a potential obtained from an output terminal. CONSTITUTION:Between power supply and ground, an n-channel MOST 11 and a p-channel MOST 12 whose size is smaller than an n-channel MOST 3 and a p-channel MOST 2 are provided in series. An input signal connection terminal 6 is connected in common to a gate of the n-MOST 11 and the p- MOST 12 and a connecting point N3 between the source of the nMOST 11 and the source of pMOST 12 connects to an output section N2 of an output buffer 1. In such a case, the potential of an output signal OUT is monitored to turn on either of the pMOST 2 and the nMOST 3 based on H, L level of the output signal OUT. The ON/OFF control of the pMOST 2 and the nMOST 3 is implemented by using a NAND gate 7 and a NOR gate 8. Thus, the possibility of simultaneous ON of the pMOST 2 and the nMOST 3, that is, the possibility of flow of through-current to the output buffer 1 is made zero.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer circuit that can reduce through current.

[Conventional technology]

FIG. 3 is a circuit diagram showing a conventional output buffer circuit.

As shown in the figure, the output buffer 1 consists of p-channel MO8) transistors (hereinafter referred to as "pMO3T") connected in series.
It's called J. ) 2 and an n-channel MOS transistor (hereinafter referred to as "nMOSTJ") 3.The input section N1 of this output buffer 1 is connected to the output of an output buffer driving inverter 4. , the output section N2 is connected to the output terminal 5. Further, the input of the inverter 4 is connected to the input signal connection terminal 6.

FIG. 4 is a timing diagram showing the operation of the output buffer circuit shown in FIG. 3. In the figure, IN indicates an input signal applied to the input signal connection terminal 6, S4 indicates an output signal of the inverter 4, and OUT indicates an output signal obtained from the output terminal 5.

As shown in the figure, the input signal IN is delayed by a time Δ by passing through the inverter 4, and appears as the output signal OUT.

Generally, the output buffer 1 is designed to allow a large current to flow in order to drive an external signal. On the other hand, when the signals applied to the gates of pMO8T2 and nMO8T3 of output buffer 1 are the same (in the example of FIG. 3, the output signal S4 of inverter 4) as in the example of FIG. 3, when the potential of this signal is inverted,
There is a period in which both the pMO8T2 and the nMOST3 are turned on, and at this moment a large through current flows between the power supply and ground.

This through current causes a voltage drop inside the IC including the output buffer 1, which has the disadvantage that it may lead to malfunction, especially when the outputs of a large number of output buffers change at the same time.

For example, there is an output buffer circuit shown in FIG. 5 to avoid this drawback. As shown in FIG. 5, the signals input to the gates of pMO3T2 and nMOS T3 of output buffer 1 are separated, and the output signal S7 of NAND gate 7 is input to the gate input of pMO8T2.
The output signal S of NOR gate 8 is input to the gate input of S T 3.
The output buffer 1 is connected to a NAND gate 7 and a NOR gate 8 so that a signal 8 is input.

The input signals of the NAND gate 7 and the NOR gate 8 are the same, - the universal input is the input signal IN, and the other input is the input signal IN or the two inverters 9, 1 connected in series.
The signal S] obtained through 0 is 0.

FIG. 6 is a timing diagram showing the operation of the output buffer circuit shown in FIG. In addition, in the same figure, T2. T3
are pMO8T2., respectively. nM.

This shows the on/off state of Sr1.

As shown in the figure, the output signal SIO of the inverter 10, which is the other input of the NAND gate 7 and the NOR gate 8, is passed through the inverters 9 and 10 for a time of 2Δ.
It is delayed from the input signal IN which is one input of the NAND gate 7 and the NOR gate 8. Therefore, the input signal IN
When the input signal IN changes from "L" to "H", the output signal S8 of the NOR gate 8 falls to the "L" level 2Δ earlier than the output signal S7 of the NAND gate 7, and the output signal S8 of the NOR gate 8 falls to the "L" level 2Δ earlier than the output signal S7 of the NAND gate 7.
”-“L” change, the signal S7 is 2Δ lower than the signal S8.
rises to “H” level quickly.

Therefore, the signal S7. 2 at the rising and falling times of S8
Since a time difference of Δt occurs, the signal S7. S8 is input to each gate pMO3T2゜n M OS T
3 are prevented from turning on at the same time.

[Problem to be solved by the invention]

However, the delay time 2Δt caused by passing through the inverters 9 and 10 depends on the threshold voltage of the transistors constituting the inverters 9'10, the gate oxide film thickness, etc.
It fluctuates due to manufacturing factors and the influence of the operating environment such as power supply voltage and temperature.

For this reason, it is not possible to obtain the desired delay time accurately.
There is a possibility that the nMOS T 2 and the pMO8T3 are turned on at the same time, and there is a problem that the through current of the output buffer 1 cannot be reliably avoided.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain an output buffer circuit that reliably prevents a through current from flowing through the output buffer.

[Means to solve the problem]

The output buffer circuit according to the present invention has input and output terminals, first and second power supplies, and a transistor size capable of supplying a large current, and one electrode is connected to the first and second power supplies, respectively. It consists of first and second transistors whose other electrodes are commonly connected to the output terminal, and when the first transistor is turned on, a signal at a first voltage level defined by the first power source is transmitted to the output terminal. an output buffer that outputs a signal at a second voltage level defined by the second power source to the output terminal when the second transistor is turned on; a potential setting means for guiding the potential of the output terminal to the first or second voltage level based on the voltage level; a first control means that controls on/off of the first transistor based on the above-mentioned voltage and turns off the first transistor in other cases; in the case of a second power supply level, controlling on/off of the second transistor based on the potential of the input signal;
and second control means that turns off the second transistor in other cases.

[Effect]

The first control means in this invention detects the potential of the output terminal, and when the potential is at the first voltage level, controls on/off of the first transistor based on the potential of the input signal; In this case, the first transistor is turned off, and on the other hand, the second control means detects the potential of the output terminal, and when the potential is at the second voltage level, the second control means detects the potential of the output terminal, and when the potential is at the second voltage level, the second control means detects the potential of the output terminal. Turning on the second transistor.

In other cases, the second transistor is turned off.

Therefore, there is no possibility that the first and second transistors are turned on at the same time.

〔Example〕

FIG. 1 is a circuit diagram showing an output buffer circuit as an embodiment of the present invention. As shown in the figure, pMO3T2. nMO8T has a smaller transistor size (gate width/gate length) than nMO3T3
11 (power supply side) and 9MO8T12 (ground side) are provided in series.

These n M OS T 11 , p M OS
The input signal connection terminal 6 is commonly connected to the gates of T12. Further, a connection point N3 between the source of the nMOST 11 and the source of the 9MO8T12 is connected to the output section N2 of the output buffer 1.

Output of NAND gate 7, NOR gate 8 ~ Output terminal 5
The configuration leading to NAND gates 7 and N is the same as that of the conventional example shown in FIG. 5, and the explanation thereof will be omitted.

The output terminal 5 is connected to the connection point N3 so that the output signal of the output buffer 1 becomes the output signal OUT of the output buffer 1, unlike the conventional one.

FIG. 2 is a timing diagram showing the operation of the output buffer circuit shown in FIG. 1. The operation will be explained below with reference to the same figure.

When the input signal IN falls from "H" to "L", one input of the NAND gate 7 becomes "L", so its output signal S
7 rises to the "L"-"H" level. As a result, pMO3T2, which was in the on state, is turned off. Furthermore, since the other input of the NOR gate 8 (output signal 0UT) is "H", its output signal S8 remains "L", and n M O
ST3 maintains the off state.

On the other hand, as the input signal IN falls, nM O5Tl
l, 9MO8T12 is switched on and off, n M
OS T 11 is turned off and pMO3T12 is turned on. As a result, the output signal OUT is guided to the "L" level by the 9MO8T12 in the on state.

Then, the output signal OUT is set to “L” by the NOR gate 8.
When the potential is lowered to a level that is recognized as "L" level, both of the two outputs of NOR gate 8 become "L" level, and the output signal S8 rises to "H" level. As a result, the n MOST3 is turned on, and an "L" level signal is outputted as output signal OUT through output buffer 1 having a large current driving capability.

When the input signal rises from “L” to “H”, the NOR gate 8
Since one of the inputs becomes “H”, its output signal S8 becomes “H”.
falls to L” level. As a result, n, which was in the on state,
MOST 3 turns off. Also, NAND gate 7
Since the other input (output signal 0UT) is "L", its output signal S7 remains "H" and pMO3T2 maintains the off state.

On the other hand, with the rise of the input signal IN, nM O5Tl
l, pMO3T12 is switched off and on, nMO8T
11 is on and pMO8T12 is off. As a result, the output signal OUT is “H” due to nMO3TII in the on state.
``Level led.

Then, the output signal OUT is output by the NAND gate 7.
When the potential rises to a level that is recognized as “H” level, the NAN
Since the two outputs of the D gate 7 both go to the "H" level, their output signals fall to the "L" level. As a result, pMO3T2, which was in the off state, is turned on, and an "H" level signal is output as the output signal OUT through the output buffer 1 having a large current driving capability.

In this way, the potential of the output signal OUT is monitored, and based on the H" and "L" levels of the output signal OUT, the pMO8T
2. Enables only one of nMO8T3 to be turned on.
pMO3T2. nMO3T3 on/off control, NA
This is done using an ND gate 7 and a NOR gate 8. Therefore, the possibility that pMO8T2 and nMO8T3 are turned on at the same time is zero. Therefore, there is no possibility that a through current will flow through this output buffer 1.

Furthermore, in order to guide the output signal OUT to a potential based on the input signal IN by the potential setting means consisting of nMO8T11' and pMO8T12, pMO3T2n MOS T
3 are both turned off, and the output part N2 of output buffer 1
Even when the output signal OUT is floating, the potential of the output signal OUT can be reliably set to the "H" or "L" level. Therefore, the period in which both pMO8T2゜nMOST3 are in the off state does not continue for a long period of time.

Note that when the input signal IN rises and falls, nMO8T
II, a through current flows between the power supply and ground through pMO3T12, but nMO3T11. Since the transistor size of pMO8T12 is sufficiently small, this does not pose much of a problem.

Also, n M OS T 11 , p M OS T
The threshold voltage of 12 is p M OS T 2 , n
When both MOS T3 are off, NAND game) 7. The output signal OUT is set to “H” by the NOR gate 8.
IIL” is set at a level that can be recognized.

〔Effect of the invention〕

As explained above, according to the present invention, the first and second control means, based on the potential obtained from the output terminal,
The first . Since the second transistors are controlled so that they are not turned on at the same time, no through current flows through the output buffer.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an output buffer circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the output buffer circuit shown in FIG. 1, and FIGS. 4 is a timing diagram showing the operation of the output buffer circuit shown in FIG. 3, and FIG. 6 is a timing chart showing the operation of the output buffer circuit shown in FIG. 5. In the figure, 1 is an output buffer, 2 is a pMO3T, 3 is an nMOST, 5 is an output terminal, 6 is an input signal connection terminal, 7 is a NAND gate, 8 is a NOR gate, and 11 is an nMOST.
MO8T, 12 is pMO3T. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) It has input and output terminals, first and second power supplies, and a transistor size capable of supplying a large current, one electrode is connected to the first and second power supplies, respectively, and the other electrode is the output terminal. The first transistor includes first and second transistors connected in common to the first transistor, and when the first transistor is turned on, it outputs a signal at a first voltage level defined by the first power source to the output terminal, and When the second transistor is turned on, the second transistor defined by the second power supply is turned on.
an output buffer that outputs a signal at a voltage level to the output terminal; and potential setting means for guiding the potential of the output terminal to the first or second voltage level based on the potential of the input signal obtained from the input terminal. , detects the potential of the output terminal, and if the potential is at the first voltage level, controls on/off of the first transistor based on the potential of the input signal; otherwise, the first transistor is turned on or off based on the potential of the input signal; a first control means for turning off the transistor; detecting the potential of the output terminal; when the potential is at the second power supply level, turning on the second transistor based on the potential of the input signal; and second control means for controlling the off state of the second transistor, and otherwise turning off the second transistor.