JPH0224273Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an improvement of a pulse width conversion transmission device.

When transmitting an analog signal, it is converted into a pulse width signal by an integral type pulse width converter and then transmitted. The integral type pulse width converter has a noise removal function, and the pulse width signal is less susceptible to noise.
This is convenient because it can be easily converted into either analog or digital signals on the receiving side.

The converter that converts the analog signal into a pulse-width signal is located close to the source of the analog signal and connected to the signal receiver by a transmission line, so that the pulse-width converter operates with as little power as possible. It is desirable to do so. Recently, due to improvements in electronic circuits, the conversion circuit itself can now operate with sufficiently low power, but since the transmission signal requires a level of, for example, several tens of milliamperes, it is difficult to output such a level. To generate the signal, pulse width conversion circuits require considerable power supply;
I was not able to reduce power consumption as I expected.

An object of the present invention is to provide a pulse width conversion transmission device that reduces power consumption while maintaining a sufficient transmission output level.

The present invention provides an integrator that integrates a continuously applied analog signal to be converted and a reference signal that is intermittently applied and has an opposite polarity and is more than twice the value of this analog signal, and an output signal of this integrator. a comparator that determines the polarity of the signal and generates an output pulse when the polarity is a predetermined one, a clock generator that generates a clock pulse of a constant period, and an output pulse of the comparator that is set by the clock pulse of this clock generator. a flip-flop circuit that is reset by a flip-flop circuit and controls the on/off of the reference signal in the integrator by its own output signal; The above object has been achieved by a pulse width conversion transmission device which is equipped with an OR gate that outputs a pulse train, and a demodulation circuit that divides the frequency of a pulse train applied from a transmission line.

Hereinafter, the present invention will be explained in detail with reference to Examples. FIG. 1 is a conceptual block diagram of an embodiment of the present invention. In FIG. 1, 1 is an integral type pulse width conversion circuit, 2 is an OR gate, 3 is a transmission line, and 4 is a demodulation circuit.

The pulse width conversion circuit 1 is a known one, and includes:
An integrator 11 that integrates the difference between the analog signal Ex to be converted and the reference signal Es, a comparator 12 that determines the polarity of the output signal, a clock generator 13, and a clock pulse of the clock generator 13. Therefore, it is set at a constant period and reset by the output signal of the comparator 12, and the reference signal of the integrator 11 is
Flip-flop circuit 1 that controls Es intermittent
It consists of 4. In such a circuit 1, the analog signal Ex is flip-flopped by a known operation.
It is converted into a pulse width output signal of the flop circuit 14.

In the conventional device, the pulse width output signal of the flip-flop circuit 14 was transmitted, but in the present invention, the clock of the clock generator 13 and the output signal of the comparator 12 are transmitted instead. I have to. Since the pulse width of the output signal of flip-flop circuit 14 is equal to the period from the occurrence of the clock pulse to the occurrence of the output pulse of comparator 12, the interval between these pulses represents the value of analog signal Ex. Both of these pulses are
Since the pulse width is extremely narrow compared to the output pulse of the flip-flop circuit 14, even if the amplitude is the same, its energy is much smaller. In other words, a pulse width converter with extremely low power consumption is realized.

The interval between the clock pulse and the output pulse of comparator 12 is such that the maximum interval does not exceed half a period of the clock pulse. Such conditions can be defined by setting the value of the reference signal Es to be twice or more the maximum value of the analog signal Ex to be converted.

The output signal of comparator 12 and the clock pulse are transmitted to the receiving side through OR gate 2 and transmission line 3.

The demodulation circuit 4 on the receiving side is a D-type flip-flop.
Consists of a flop circuit. In this flip-flop circuit, the D terminal and the output terminal on the opposite phase side are directly connected, and an input pulse is given to the T terminal.This makes it possible to convert the flip-flop circuit into a binary circuit in which the output is inverted every time an input pulse arrives. A circuit is formed. This flip-flop circuit restores the interval between the clock pulse and the output pulse of comparator 12 to a pulse width signal as shown in FIG.
The pulse width signal is either smoothed into an analog signal or digitally measured and converted into a digital signal.

Here, the demodulated output signal has opposite phases depending on whether the pulse that arrives first is the clock pulse or the output signal of comparator 12. However, since the output signal of the comparator 12 is determined not to lag behind the clock pulse by more than half a cycle, the demodulated signal is the one with the smaller duty ratio of the two output signals of the flip-flop circuit. You should adopt one. Alternatively, when one of the outputs is fixedly adopted, the digital measurement of the pulse width may be switched to complement measurement when the duty ratio becomes larger than 1/2. Since such a demodulation circuit is used, one signal transmission line can be used in common for the clock pulse and the output signal of the comparator, thereby simplifying the configuration.

Although the present invention has been described above with reference to preferred embodiments, the present invention may be implemented in various ways within the scope of the claims for utility model registration.

[Brief explanation of the drawing]

Figure 1 is a conceptual configuration diagram of an embodiment of the present invention;
The figure is an explanatory diagram of the operation of the apparatus of FIG. 1. 1... Pulse width converter, 2... OR gate, 3
...Transmission line, 4...Demodulation circuit.

Claims (1)

[Scope of utility model registration request] An integrator that integrates a continuously given analog signal to be converted and a reference signal that is intermittently given and has an opposite polarity and is more than twice the value of this analog signal, and determines the polarity of the output signal of this integrator. a comparator that generates an output pulse when the polarity is a predetermined value; a clock generator that generates a clock pulse of a constant period; and a clock generator that is set by the clock pulse of the clock generator and reset by the output pulse of the comparator. a flip-flop circuit that controls on/off of the reference signal in the integrator by its own output signal; an OR gate that outputs the logical sum of the output pulse of the comparator and the clock pulse of the clock generator to a transmission line; , and a demodulation circuit that frequency-divides a pulse train provided from a transmission line.