JPH0244446U - - Google Patents

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Publication number
JPH0244446U
JPH0244446U JP12277788U JP12277788U JPH0244446U JP H0244446 U JPH0244446 U JP H0244446U JP 12277788 U JP12277788 U JP 12277788U JP 12277788 U JP12277788 U JP 12277788U JP H0244446 U JPH0244446 U JP H0244446U
Authority
JP
Japan
Prior art keywords
output
signal sequence
data
converter
shift registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12277788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12277788U priority Critical patent/JPH0244446U/ja
Publication of JPH0244446U publication Critical patent/JPH0244446U/ja
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のデイジタルFM変復調系統図、
第2図は本考案の主要部であるデータ判定器のブ
ロツク図、第3図は本考案の主要部を示す第2図
の回路の各部波形である。 1……低域ろ波器。12……VCO、13……
伝送路、14……帯域通過ろ波器、15……周波
数弁別器、16……データ判定器、17……タイ
ミング発生器、21……AD変換器、22〜24
……シフトレジスタ、25……判定テーブル、2
6……データレジスタ。
Figure 1 is a conventional digital FM modulation/demodulation system diagram.
FIG. 2 is a block diagram of a data determiner which is the main part of the present invention, and FIG. 3 is a waveform of each part of the circuit of FIG. 2 showing the main part of the present invention. 1...Low pass filter. 12...VCO, 13...
Transmission line, 14... Bandpass filter, 15... Frequency discriminator, 16... Data determiner, 17... Timing generator, 21... AD converter, 22-24
...Shift register, 25...Judgment table, 2
6...Data register.

Claims (1)

【実用新案登録請求の範囲】 デイジタルFM変調波の受信装置における復調
回路の周波数弁別器の出力に接続されたデータ判
定器に、 該周波数弁別器の出力を一定の変換クロツクで
標本化した標本化出力をNビツトで量子化するA
D変換器と、 該AD変換器のNビツト出力の各ビツトにそれ
ぞれ割り当てられて入力するN個のM段シフトレ
ジスタと、 該N個のM段シフトレジスタからのM個の出力
の信号系列と信号間距離が最も小さい信号系列を
予め記憶された基準信号系列から読み出してデー
タ出力する判定テーブルと、 該判定テーブルの出力を判定クロツクにより外
部へ送出するためのデータレジスタと、 を備えたことを特徴とする復調回路。
[Claims for Utility Model Registration] Sampling in which the output of the frequency discriminator is sampled at a constant conversion clock in a data determiner connected to the output of the frequency discriminator of the demodulation circuit in a digital FM modulated wave receiving device. A to quantize the output by N bits
A D converter, N M-stage shift registers each assigned to each bit of the N-bit output of the AD converter for input, and a signal sequence of M outputs from the N M-stage shift registers. A determination table for reading a signal sequence with the smallest inter-signal distance from a pre-stored reference signal sequence and outputting the data, and a data register for transmitting the output of the determination table to the outside using a determination clock. Characteristic demodulation circuit.
JP12277788U 1988-09-21 1988-09-21 Pending JPH0244446U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12277788U JPH0244446U (en) 1988-09-21 1988-09-21

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12277788U JPH0244446U (en) 1988-09-21 1988-09-21

Publications (1)

Publication Number Publication Date
JPH0244446U true JPH0244446U (en) 1990-03-27

Family

ID=31371024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12277788U Pending JPH0244446U (en) 1988-09-21 1988-09-21

Country Status (1)

Country Link
JP (1) JPH0244446U (en)

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