JPH0224411B2 - - Google Patents
Info
- Publication number
- JPH0224411B2 JPH0224411B2 JP57231754A JP23175482A JPH0224411B2 JP H0224411 B2 JPH0224411 B2 JP H0224411B2 JP 57231754 A JP57231754 A JP 57231754A JP 23175482 A JP23175482 A JP 23175482A JP H0224411 B2 JPH0224411 B2 JP H0224411B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- selection
- supply device
- terminals
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000010355 oscillation Effects 0.000 claims description 15
- 239000013078 crystal Substances 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Description
【発明の詳細な説明】
本発明はクロツク供給装置に関し、特にTTL
レベルで入力される外部供給クロツクあるいは内
蔵発振回路出力を半導体集積回路内のクロツクと
して供給するクロツク供給装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock supply device, and more particularly to a TTL clock supply device.
The present invention relates to a clock supply device that supplies an externally supplied clock input at a level or the output of a built-in oscillation circuit as a clock in a semiconductor integrated circuit.
従来、この種のクロツク供給装置は、第１図に
示すように、水晶等が接続される二つの端子T2，
T3を有する発振回路１０と、TTLレベルの外部
クロツクを受ける端子T1と、この端子T1に接続
されるインバータ１１と、選択端子T4を有し、
この選択端子T4に入力される選択情報によつて
発振回路１０の出力が外部クロツクのいずれかの
信号を選択し切換える選択回路１２とを含んで構
成されていた。このようなクロツク供給装置で
は、外部端子としてT1〜T4の４本もの端子を必
要とする。外部端子にこれだけ端子が費やされる
ことは半導体集積回路の他の機能端子の割当てを
減らすことになり、半導体集積回路の性能を下げ
るという欠点を生ずる。 Conventionally, this type of clock supply device has two terminals T 2 , to which a crystal or the like is connected, as shown in FIG.
It has an oscillation circuit 10 having T3 , a terminal T1 receiving an external clock at TTL level, an inverter 11 connected to this terminal T1 , and a selection terminal T4 ,
The oscillation circuit 10 includes a selection circuit 12 which selects and switches the output of the oscillation circuit 10 to one of the external clock signals depending on the selection information inputted to the selection terminal T4 . Such a clock supply device requires as many as four terminals T1 to T4 as external terminals. The use of so many terminals for external terminals reduces the allocation of other functional terminals of the semiconductor integrated circuit, resulting in a drawback of lowering the performance of the semiconductor integrated circuit.
本発明は上記欠点を除去し、クロツク供給に費
される端子数を減らし、半導体集積回路の他の機
能に割当てられる端子数を増加させ半導体集積回
路の性能を向上せしめるのに有効なクロツク供給
装置を提供するものである。 The present invention is a clock supply device which is effective in eliminating the above drawbacks, reducing the number of terminals used for clock supply, increasing the number of terminals allocated to other functions of the semiconductor integrated circuit, and improving the performance of the semiconductor integrated circuit. It provides:
本発明のクロツク供給装置は、水晶等に接続さ
れる二つの端子を有し、かつ該端子のうちの一方
の端子が外部クロツク供給装置に接続される発振
回路と、前記一方の端子に入力端が接続して外部
クロツクを受けるインバータと、選択端子を有し
該選択端子に入力される選択情報により前記発振
回路の出力もしくは前記インバータの出力のいず
れかを選択する選択回路とを含んで構成される。 The clock supply device of the present invention has two terminals connected to a crystal or the like, an oscillation circuit having one terminal connected to an external clock supply device, and an input terminal connected to the one terminal. is connected to an inverter that receives an external clock; and a selection circuit that has a selection terminal and selects either the output of the oscillation circuit or the output of the inverter based on selection information input to the selection terminal. Ru.
次に本発明の実施例について図面を用いて説明
する。 Next, embodiments of the present invention will be described using the drawings.
第２図は本発明の一実施例のブロツク図であ
る。 FIG. 2 is a block diagram of one embodiment of the present invention.
この実施例のクロツク供給装置は、水晶等に接
続される二つの端子T11，T12を有し、かつこれ
らの端子のうちの一方の端子T11が外部クロツク
供給装置に接続される発振回路２０と、端子T11
に入力端が接続して外部クロツクを受けるインバ
ータ１１と、選択端子T4を有し、選択端子T4に
入力される選択情報により発振回路２０の出力も
しくはインバータ１１の出力のいずれかを選択す
る選択回路１２とを含んで構成される。 The clock supply device of this embodiment is an oscillation circuit that has two terminals T 11 and T 12 connected to a crystal etc., and one terminal T 11 of these terminals is connected to an external clock supply device. 20 and terminal T 11
It has an inverter 11 whose input terminal is connected to receive an external clock, and a selection terminal T4 , and selects either the output of the oscillation circuit 20 or the output of the inverter 11 according to selection information input to the selection terminal T4 . The selection circuit 12 is configured to include a selection circuit 12.
発振回路２０の出力を半導体集積回路内のクロ
ツクとする場合は、端子T11，T12に水晶を接続
し、選択端子T4に論理「１」を与えれば発振回
路２０の出力をクロツクとすることができる。 When using the output of the oscillation circuit 20 as a clock in the semiconductor integrated circuit, connect a crystal to the terminals T 11 and T 12 and apply logic "1" to the selection terminal T 4 to use the output of the oscillation circuit 20 as the clock. be able to.
外部クロツクの場合は、端子T11の外部クロツ
ク信号を供給すれば、インバータ１１の出力をク
ロツクするべく選択端子T4を論理「０」にすれ
ば良い。このように発振回路２０の一方の端子
T11と共通にインバータ１１の入力端子として
T11を使用することによりクロツク供給装置の端
子数を一つ減らすことができる。一つ減つた分だ
け半導体集積回路に他の機能を割当てることがで
き性能を向上させることができる。 In the case of an external clock, if the external clock signal at terminal T11 is supplied, selection terminal T4 may be set to logic "0" in order to clock the output of inverter 11. In this way, one terminal of the oscillation circuit 20
Commonly used as input terminal of inverter 11 with T11
By using T11 , the number of terminals in the clock supply device can be reduced by one. Other functions can be assigned to the semiconductor integrated circuit by one less function, and the performance can be improved.
以上詳細に説明したように、本発明によれば、
所要端子数を減らし、減らした分の端子を半導体
集積回路の他の機能用に割当てることのできるク
ロツク供給装置が得られるのでその効果は大き
い。 As explained in detail above, according to the present invention,
This is highly effective because it provides a clock supply device that can reduce the number of required terminals and allocate the reduced number of terminals to other functions of the semiconductor integrated circuit.
第１図は従来のクロツク供給装置の一例のブロ
ツク図、第２図は本発明の一実施例のブロツク図
である。
１０……発振回路、１１……インバータ、１２
……選択回路、２０……発振回路、T1……外部
クロツクを受ける端子、T2，T3……端子、T4…
…選択端子、T11，T12……端子。
FIG. 1 is a block diagram of an example of a conventional clock supply device, and FIG. 2 is a block diagram of an embodiment of the present invention. 10...Oscillation circuit, 11...Inverter, 12
...selection circuit, 20 ... oscillation circuit, T 1 ... terminal for receiving external clock, T 2 , T 3 ... terminal, T 4 ...
...selection terminal, T 11 , T 12 ... terminal.
Claims (1)
該端子のうちの一方の端子が外部クロツク供給装
置に接続される発振回路と、前記一方の端子に入
力端が接続して外部クロツクを受けるインバータ
と、選択端子を有し該選択端子に入力される選択
情報により前記発振回路の出力もしくは前記イン
バータの出力のいずれかを選択する選択回路とを
含むことを特徴とするクロツク供給装置。1 An oscillator circuit having two terminals connected to a crystal etc., one of which is connected to an external clock supply device, and an oscillation circuit with an input terminal connected to the one terminal to supply an external clock. 1. A clock supply device comprising: an inverter that receives the signal; and a selection circuit that has a selection terminal and selects either the output of the oscillation circuit or the output of the inverter based on selection information input to the selection terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57231754A JPS59122017A (en) | 1982-12-27 | 1982-12-27 | Clock supply device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57231754A JPS59122017A (en) | 1982-12-27 | 1982-12-27 | Clock supply device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59122017A JPS59122017A (en) | 1984-07-14 |
| JPH0224411B2 true JPH0224411B2 (en) | 1990-05-29 |
Family
ID=16928506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57231754A Granted JPS59122017A (en) | 1982-12-27 | 1982-12-27 | Clock supply device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59122017A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0172733U (en) * | 1987-11-04 | 1989-05-16 |
-
1982
- 1982-12-27 JP JP57231754A patent/JPS59122017A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59122017A (en) | 1984-07-14 |
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