JPS59122017A - Clock supply device - Google Patents
Clock supply deviceInfo
- Publication number
- JPS59122017A JPS59122017A JP57231754A JP23175482A JPS59122017A JP S59122017 A JPS59122017 A JP S59122017A JP 57231754 A JP57231754 A JP 57231754A JP 23175482 A JP23175482 A JP 23175482A JP S59122017 A JPS59122017 A JP S59122017A
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- supply device
- terminals
- oscillation circuit
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010355 oscillation Effects 0.000 claims abstract description 18
- 239000013078 crystal Substances 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 4
- 241001494479 Pecora Species 0.000 description 1
- 238000009412 basement excavation Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はクロック供給装置に関し、特にＴＴＬレベルで
入力される外部供給クロックあるいは内蔵発掘回路出力
を半導体集積回路内のクロックとして供給するクロック
供給装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock supply device, and more particularly to a clock supply device that supplies an externally supplied clock input at TTL level or the output of a built-in excavation circuit as a clock in a semiconductor integrated circuit.
従来、この種のクロック供給装置は、第１図に示すよう
に、水晶等が接続される二つの端子Ｔ 、。Conventionally, this type of clock supply device has two terminals T to which a crystal or the like is connected, as shown in FIG.
Ｔ３を有する発振回路１０と、ＴＴＬレベルの外部クロ
ックを受ける端子ＴＩと、この端子Ｔ１に接続されるイ
ンバータ１１と、選択端子Ｔ４を有し、この選択端子Ｔ
４に入力される選択情報によって発振回路１０の出力か
外部クロックのいずれかの信号を選択し切換える選択回
路１２とを含んで構成されていた。このようなりロック
供給装置では、外部端子としてＴ１〜Ｔ４の４本もの端
子を必要とする。外部端子にこれだけ端子が費やされる
ことは半導体集積回路の他の機能端子の割当てを減らす
ことになり、半導体集積回路の性能を下げるという欠点
を生ずる。It has an oscillation circuit 10 having T3, a terminal TI that receives an external clock at TTL level, an inverter 11 connected to this terminal T1, and a selection terminal T4.
4, and a selection circuit 12 that selects and switches between the output of the oscillation circuit 10 and the external clock signal according to selection information input to the oscillation circuit 10. Such a lock supply device requires as many as four terminals T1 to T4 as external terminals. The use of so many terminals for external terminals reduces the allocation of other functional terminals of the semiconductor integrated circuit, resulting in a drawback of lowering the performance of the semiconductor integrated circuit.
本発明は上記欠点を除去し、クロック供給に費される端
子数を減らし、半導体集積回路の他の機能に割当てられ
る端子数を増加させ半導体集積回路の性能を向上せしめ
るのに有効なりロック供給装置を提供するものである。The present invention eliminates the above drawbacks, reduces the number of terminals used for clock supply, increases the number of terminals allocated to other functions of the semiconductor integrated circuit, and is effective in improving the performance of the semiconductor integrated circuit. It provides:
本発明の、クロック供給装置は、水晶等に接続される二
つの端子を有し、かつ該端子のうちの一方の端子が外部
クロック供給装置に接続される発振回路と、前記一方の
端子に入力端が接続して外部クロックを受けるインバー
タと、選択端子を有し該選択端子に入力される選択情報
によシ前記発振回路の出力もしくは前記インバータの出
力のいずれかを選択する選択回路とを含んで構成される
。The clock supply device of the present invention has two terminals connected to a crystal or the like, and includes an oscillation circuit to which one terminal of the terminals is connected to an external clock supply device, and an oscillation circuit that is input to the one terminal. an inverter connected at one end to receive an external clock; and a selection circuit having a selection terminal and selecting either the output of the oscillation circuit or the output of the inverter according to selection information input to the selection terminal. Consists of.
次に本発明の実施例について図面を用いて説明する。Next, embodiments of the present invention will be described using the drawings.
第２図は本発明の一実施例のブロック図である。FIG. 2 is a block diagram of one embodiment of the present invention.
この実施例のクロック供給装置−１水晶等に接続される
二つの端子Ｔ’ｔｔ 、 Ｔ１２を有し、かつこれらの
端子のうちの一方の端子Ｔｌｌが外部クロック供給装置
に接続される発振回路２０と、端子’Ｉ’ｌｌに入力端
が接続して外部クロックを受けるインバータ１１と、選
択端子Ｔ４を有し、選択端子Ｔ４に入力される選択情報
により発振回路２０の出力もしくはインバータ１１の出
力のいずれかを選択する選択回路１２とを含んで構成さ
れる。Clock supply device of this embodiment-1 An oscillation circuit 20 having two terminals T'tt and T12 connected to a crystal etc., and one terminal Tll of these terminals connected to an external clock supply device. , an inverter 11 whose input terminal is connected to the terminal 'I'll to receive an external clock, and a selection terminal T4. The configuration includes a selection circuit 12 that selects one of the two.
発振回路２０の出力を半導体集積回路内のクロックとす
る場合は、端子Ｔ１１ ｚ ＴＩｔに水晶を接続し、選
択端子Ｔ４に論理「１」を与えれば発振回路２０の出力
をクロックとすることができる。When the output of the oscillation circuit 20 is used as a clock in the semiconductor integrated circuit, the output of the oscillation circuit 20 can be used as the clock by connecting a crystal to the terminal T11 z TIt and applying logic "1" to the selection terminal T4. .
外部クロックの場合は、端子Ｔｌｌに外部クロック信号
を供給すれば、インバータ１１の出力をクロックするべ
く選択端子Ｔ４を論理「０」にすれば良い。このように
発振回路２０の一方の端子Ｔ。In the case of an external clock, if the external clock signal is supplied to the terminal Tll, the selection terminal T4 may be set to logic "0" in order to clock the output of the inverter 11. In this way, one terminal T of the oscillation circuit 20.
と共通にインバータ１１の入力端子として’Ｉ’ｌｌを
使用することによシクロツク供給装置の端子数を一つ減
らすことができる。一つ減った分だけ半導体集積回路に
他の機能を割当てることができ性能を向上させることが
できる。By using 'I'll as the input terminal of the inverter 11 in common with the above, the number of terminals of the cyclic supply device can be reduced by one. Other functions can be assigned to the semiconductor integrated circuit by one less function, and performance can be improved.
以上詳細に説明したように、本発明によれば、所要端子
数を減らし、減らした分の端子を半導体集積回路の他の
機能用に割当てることのできるクロック供給装置が得ら
れるのでその効果は太きい。As described in detail above, according to the present invention, it is possible to obtain a clock supply device that can reduce the number of required terminals and allocate the reduced number of terminals to other functions of the semiconductor integrated circuit, so that the effect is significant. Hey.
第１図は従来のクロック供給装置の一例のブロック図、
第２図は本発明の一実施例のブロック図である。
１０・・・・・・発振回路、１１・・・・・・インバー
タ、１２・・・・・・選択回路、２０・・・・・・発振
回路、Ｔｌ・・・・・・外部クロックを受ける端子、Ｔ
、、Ｔ、−・・・・・・端子、Ｔ４・・・・・・選択端
子、’Ｉ’ｌｌ 、 Ｔｌｌ°°団°端子。
Ｉ
単ｌ 園
１
羊２ 図FIG. 1 is a block diagram of an example of a conventional clock supply device.
FIG. 2 is a block diagram of one embodiment of the present invention. 10...Oscillation circuit, 11...Inverter, 12...Selection circuit, 20...Oscillation circuit, Tl...Receives external clock terminal, T
,, T, -... terminal, T4... selection terminal, 'I'll, Tll°° group ° terminal. I Single Garden 1 Sheep 2 Diagram
Claims (1)
ちの一方の端子が外部クロック供給装置に接続される発
振回路と、前記一方の端子に入力端が接続して外部クロ
ックを受けるインバータと、選択端子を有し該選択端子
に入力される選択情報によシ前記発振回路の出力もしく
は前記インバータの出力のいずれかを選択する選択回路
とを含むことを特徴とするクロック供給装置。An oscillation circuit having two terminals connected to a crystal etc., one of which is connected to an external clock supply device, and an input terminal connected to the one terminal to receive an external clock. A clock supply device comprising: an inverter; and a selection circuit having a selection terminal and selecting either the output of the oscillation circuit or the output of the inverter according to selection information input to the selection terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57231754A JPS59122017A (en) | 1982-12-27 | 1982-12-27 | Clock supply device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57231754A JPS59122017A (en) | 1982-12-27 | 1982-12-27 | Clock supply device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59122017A true JPS59122017A (en) | 1984-07-14 |
| JPH0224411B2 JPH0224411B2 (en) | 1990-05-29 |
Family
ID=16928506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57231754A Granted JPS59122017A (en) | 1982-12-27 | 1982-12-27 | Clock supply device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59122017A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0172733U (en) * | 1987-11-04 | 1989-05-16 |
-
1982
- 1982-12-27 JP JP57231754A patent/JPS59122017A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0172733U (en) * | 1987-11-04 | 1989-05-16 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0224411B2 (en) | 1990-05-29 |
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