JPH02244249A - General-purpose centronics interface controller - Google Patents

Abstract

PURPOSE:To flexibly cope with such the case a centronics interface device to be connected outputs the handshake signals in different timings by providing with a timing setting part to selectively and variably set the output timings among control signals. CONSTITUTION:A timing setting part 10 sets previously the rising/falling timings of the control signals forming the handshake signals in accordance with the characteristics of a partner centronics interface device 3. Then a timer, etc., of a handshake signal output part 20 are controlled and the handshake signals are outputted in the set timings respectively. If the device 3 is replaced with another one having a different standard, the part 20 changes the set timing. As a result, the working timings of the handshake signals are variably set to cope with various types of devices 3.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a general-purpose Centronics interface control device that controls a Centronics interface, which is widely used in printers, XY plotters, and the like.

(Prior Art) Centronics interfaces are widely used when data is transferred between a personal computer and an XY plotter, or between a word processor and a printer. This Centronics interface transfers data in parallel in one direction, and in order to control the transfer,
A so-called handshake signal is exchanged.

FIG. 2 shows a general system configuration diagram connected via a Centronics interface.

In the figure, a Centronics interface control device 1 built in a personal computer M1 or the like is connected to a Centronics interface control device 2 built in a printer 2 or the like via a Centronics interface 3 of a predetermined standard.

Handshake signals output from the Centronics interface control device 1 to the Centronics interface device 2 via the Centronics interface 3 include, for example, a DATAENB signal that is activated during a data transfer operation, and a DATAENB signal that is activated at a predetermined timing during the data transfer operation. There is a DATAASTB signal that is activated.

Further, as a handshake signal output from the Centronics interface device 2 side to the Centronics interface control device 1 side, there is an ACK signal for data reception response.

The basic configuration of the Centronics interface as described above is standardized. However, the output timing of individual signals is left to each device manufacturer.

Therefore, in reality, the handshake signal varies from manufacturer to manufacturer.

The output timing, length, etc. of the handshake signals vary, and for example, when connecting printers to one personal computer, it may not be possible to operate the printer correctly if the printer is made by a different manufacturer.Therefore, in general, the handshake signal Mutual connection is possible only when the output timings match.

(Problem to be Solved by the Invention) However, for example, when expanding the system or replacing devices such as printers that make up part of the system, only devices with matching handshake signal output timings are compatible. If there is no such option, the degree of freedom of choice will be limited.

Conventionally, therefore, a method has been adopted in which the Centronics interface control device built into the personal computer is replaced with a dedicated one in accordance with the standards of the Centronics interface device on the equipment side. However, replacing or adding such circuit parts is complicated,
Poor scalability.

The present invention has been made with attention to the above points, and an object of the present invention is to provide a general-purpose Centronics interface control device that can variably set the operation timing of the handshake signal so as to be compatible with various Centronics interface devices. It is something to do.

(Means for Solving the Problems) A general-purpose Centronics interface control device of the present invention includes a circuit that generates a handshake signal for a Centronics interface that is a combination of a plurality of control signals. The present invention is characterized in that it includes a timing setting section that selectively and variably sets the timing, and a handshake signal output section that outputs each of the control signals in a predetermined order at the set timing.

(Operation) In the above-described device, the timing setting section presets the rise and fall timings of each control signal constituting the handshake signal in accordance with the characteristics of the other party's Centronics interface device. Then, control the timer etc. of the handshake signal output section and output the handshake signal at the set timing.If the other party's Centronics interface device is replaced with one of a different standard, the above All you have to do is change the settings in the timing setting section.

(Example) Hereinafter, the present invention will be explained in detail using embodiments shown in the drawings.

FIG. 1 is a block diagram of an embodiment of the general purpose Centronics interface controller of the present invention.

The illustrated device is connected via a Centronics interface 3 to the Centronics interface device shown in FIG. This device includes a timing setting section 10, a handshake signal output section 20, and an input/output board 30.

The timing setting unit 10 is composed of a microprocessor, a clock generator, etc., and supplies the reference clock K to each circuit block of the handshake output unit 20 and the input/output board 30, and also controls a timer that determines the handshake signal output timing. Operating time TI, T2. T3. T4. T5
Generate and output. These operating times T1 to T5 are set by, for example, a several-bit digital signal. These values are input and set from the memory of the processor built in the timing setting section 10, a key switch for inputting setting data, or the like.

Further, the timing setting unit 10 outputs a load signal in order to load each operating time Tl-75 set and output in this way into a timer circuit forming the handshake signal output unit 20.

Furthermore, when data is actually transferred via the Centronics interface 3, a transfer start signal S instructing to start the transfer is output at a predetermined timing.

Next, the handshake signal output section 20 has five timer circuits and two OR gates.

That is, the timer circuit includes T1 timer 21. T2 timer 22
．． T3 timer 23. T4 timer 24 and T5 timer 25
Consists of. Each timer has four input terminals and one output terminal.The top input terminal of each timer in Figure 0 is the load terminal, and the operating time TINT5 input to the second input terminal from the top is It is loaded by the load signal input to the top terminal. The third input terminal from the top is a terminal that accepts a timer start instruction. Further, the bottom input terminal is a terminal for resetting a timer. Also,
The output terminal of each timer 21 to 25 is set to 1 after time-up.
It is configured so that the output signal rises by the clock.

Note that the third input terminal from the top of the T1 timer 21 in the figure is connected so that the output of the OR gate 26 is input thereto. The transfer start signal S output from the timing setting section 10 is inputted to one terminal of the OR gate 26, and the output ■ of the T4 timer 24 is inputted to the other terminal. Therefore, T
The I timer 21 is started (timer started) by the output of the OR gate 26.

In addition, the output ■ of the TI timer 21 is input to the fourth terminal from the top of the T1 timer 21, the third input terminal from the top of the T2 timer 22, and the third input terminal from the top of the T5 timer 25.
input to the second input terminal. Therefore, the T1 timer 21 is reset at the same time as the T1 timer 21 times up, and the T2 timer 22 and the T5 timer 25 are both started at the same time as the T1 timer 21 times up.

The output ■ of the T2 timer 22 is 4 from the top of the T2 timer 22.
3 from the top of the T3 timer 23.
input to the second terminal. As a result, the T2 timer 22 is reset immediately after the time-up, and the T3 timer 23 is started when the T2 timer 22 times up. T3
The output ■ of the timer 23 is input to the fourth input terminal from the top of the T3 timer 23. Therefore, the T3 timer 23 is also reset at the same time as time-up.

The above T1 timer 21. The T2 timer 22 and the T3 timer 23 output the DATA via the input/output boat 3o.
It is provided to control the falling and rising edges of the ENB signal and the DATAASTB signal. This DAT
The AENB signal and the DATAASTB signal constitute a handshake signal, and both are used in a low active state.

On the other hand, the T4 timer 24 is used to receive the ACK signal input from the Centronics interface 3 to the input/output port 30 and perform timing control to newly raise the DATAENB signal at a predetermined timing. That is, the T4 timer 24 is activated by the ACK signal input from the input/output board 30, and its output ■ is input to the fourth terminal from the top of the T4 timer 24 to reset itself, and is output to the OR gate 26. and T1
Start timer 21.

The T5 timer 25 is provided to output an error signal ERR, assuming that some fault has occurred, if the ACK signal is not input from the Centronics interface 3 within a predetermined time after the DATAASTB signal falls. . Therefore, as described above, the T5 timer 25 accepts the output of the T1 timer 21 and starts when the timer reaches its time, and is reset by the ACK signal input from the input/output boat 30 via the OR gate 27. Also, if the ACK signal is not input, T5 timer 2
5 times up, outputs an error signal ERR, and resets the T5 timer 25 itself via the OR gate 27.

The input/output boat 30 has three latch circuits 31 to 33 and 1
It is composed of two AND gates 34.

The latch circuit 31 receives the output of the OR gate 26 of the handshake signal output section 20 into the set terminal, receives the output of the T3 timer 23 into the reset terminal, and outputs the output from the DAT.
It is used as the AENB signal. Further, the latch circuit 32 has T
They are wired so that the output (2) of the T2 timer 21 is received at the set terminal, the output (2) of the T2 timer 22 is accepted at the reset terminal, and the DATAASTB signal is output from the mutual terminal.

Finally, the latch circuit 33 is wired so that the set terminal receives the ACK signal, and the output of the alternate terminal is input to the AND gate 34. The AND gate 34 performs a logical product of the ACK signal and the output of the latch circuit 33, and outputs this to the OR gate 27 of the handshake signal output section 20.

The apparatus having the above configuration operates as follows.

FIG. 3 is an operation timing chart of the device of the present invention.

In the figure, the reference clock shown in Figure 1 is output at a constant cycle as shown [Figure 3 (a)],
This reference clock controls a counter built in each timer circuit 21 to 25, and a latch circuit 31, 32, 33.
controls the output timing.

First, prior to the operation of the apparatus, an operating time Tl is set in advance by the timing setting section 10 of FIG.

T2. T3. T4. T5 is T I timer 21, respectively.
, T2 timer 22. T3 timer 23. It is input to the T4 timer 24 and T5 timer 25 and loaded by the load signal.

Next, a data transfer operation is actually started via the Centronics interface 3. At the start, first, as shown in FIG. 3(b), a transfer start signal S is output. This signal is transmitted to the OR gate 26 shown in FIG.
The signal is input to the T1 timer 21 via the T1 timer 21. As a result, the output of the latch circuit 31 falls with a one-clock delay. This becomes the DATAENB signal shown in FIG. 3(c).

Here, as explained earlier, the T1 timer 21 is started, and at the same time as its time-up, the output of the T1 timer 21 is
rises for one clock [Fig. 3(d)], and when the output ■ of the TI timer 21 rises, the output of the latch circuit 32 falls exactly one clock later, and this is the output of the latch circuit 32.
This becomes the TASTB signal [Fig. 3(e)]. After that, data transfer is performed, but when the T2 timer, which was activated at the same time as the time-up of the TI timer 21, counts up, its output rises by one clock [Figure 3 (f)]
. As a result, the latch circuit 32 is reset, and the DATA
The STB signal rises [Fig. 3(e)]. And T
The T3 timer, which was started at the same time as the time-up of the second timer, times up after 13 hours and rises by one clock [FIG. 3(g)]. When the T3 timer output ■ rises, the latch circuit 31 is reset and the DATA
The ENB signal rises [Figure 3 (C)].

As described above, two types of handshake signals are output from the input/output boat 30 to the Centronics interface 3.

On the other hand, from Centronics Interface 3,
As a response, the ACK signal is input to the latch circuit 33 [Fig. 3 (h)], and when the ACK signal rises, the output ■ of the AND gate 34 rises [Fig. 3 (i)]
, the T4 timer 24 is started. As a result, the T4 timer 24 times up after T4 hours, and its output ■ rises by one clock [FIG. 3 (j)]. The DATAENB signal is input to the set terminal of the latch circuit 31 through the DATAENB signal.
Figure 3 (C)].

Data transfer is executed by repeating the above operations.

On the other hand, the T5 timer 25 started at the same time as the T1 timer 21 counts up, as shown in FIG.
A 5-hour clock is carried out. And during this time ACK
If the signal [Fig. 3 (h)] is not input, timer 2
5 times up, its output rises by one clock as shown by the broken line [FIG. 3(k)], and this is output to the external circuit as an error signal ERR. Furthermore, the error signal E
When RR is output, as shown by the broken line in Fig. 3, the ACK signal [Fig. 3 (h)], the AND gate output [Fig. 3 (i)], and the T4 timer output [Fig. )], nothing changes.

Note that the transmission data is set by a host device (not shown) while the DATAENB signal is rising.

The present invention is not limited to the above embodiments.

The configuration for controlling the rise and fall timings of each control signal constituting the handshake signal can be realized by various program timers, gate circuits, etc. in addition to the above configuration. Further, the operation time for setting the handshake signal timing set in the timing setting section 10 can be set using a mechanical switch such as a dip switch, a programmable read-only switch, or a programmable read-only switch.
Various operating times may be stored in a memory or the like for various types of Centronics interface devices known in advance, which may be selected and switched by a storage element such as a memory (FROM), and may be switched as needed. If one is selected and used, a highly versatile interface control device that can be easily switched can be obtained.

(Effects of the Invention) According to the general-purpose Centronics interface control device of the present invention described above, it is possible to flexibly cope with the case where the connected Centronics interface devices output handshake signals at different timings. Moreover, since the settings can be easily changed by changing switches, etc., it is effective in expanding and changing the system. Furthermore, there is no need to prepare separate dedicated Centronics interface control devices, and costs can be reduced by standardizing device parts.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of a general-purpose centronics interface control device of the present invention, FIG. 2 is a block diagram showing a general system configuration, and FIG. 3 is an operation timing chart of the device of the present invention. 3... Centronics interface, 10... Timing setting unit, 20... Handshake output unit, 21-25... Timer circuit, 26.27... OR gate, 30... Input/output board, 31 ~33... Latch circuit, 34... AND gate.

Claims (1)

[Scope of Claim] A circuit for generating a handshake signal for a Centronics interface that is formed by combining a plurality of control signals, comprising: a timing setting section that selectively and variably sets the output timing between the respective control signals; A general-purpose centronics interface control device, comprising: a handshake signal output section that outputs each of the control signals in a predetermined order at the set timing.