JPH0224424B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hands-free circuit used for making loudspeaking calls using a microphone and a speaker.

[Conventional technology]

Function telephones with various special functions, key telephones for key telephone devices, intercoms, etc. are equipped with a hands-free circuit for loudspeaker calls. Taking a telephone as an example, the block diagram in Figure 2 shows The configuration shown is commonly used.

In other words, the transmission signal from microphone 1 is
It is amplified by a preamplifier (hereinafter referred to as HA) 2, passed through a variable loss circuit (hereinafter referred to as VLS) 3, and then amplified again by a transmitter amplifier (hereinafter referred to as TA) 4 before being connected to a sidetone prevention circuit (hereinafter referred to as HYB). ) given to 5;
Here, the receiving signal is blocked from being transmitted to the receiving side and sent to a two-wire telephone line (hereinafter referred to as line) 6, while the received signal from line 6 is amplified by a receiving amplifier (hereinafter referred to as RA) 7. After that, VLS・8
The signal is amplified to a predetermined power by a power amplifier (hereinafter referred to as PA) 9 to drive a speaker 10.

However, from TA/4 side by HYB/5, RA/
It is difficult to make the amount of crosstalk attenuation to the 7 side sufficiently large, and a control unit 11 is provided to prevent the generation of noise due to acoustic coupling between the speaker 10 and the microphone 1.・12 and 1
Compare the levels of the transmitting signal and the receiving signal via VLS 3, judge the signal on the high level side, and if the transmitting signal is high, reduce the loss of VLS 3.
In addition to increasing the loss of VLS-8, VLS-13
is controlled as exhibiting a predetermined loss, while
If the level of the received signal is high, the loss of VLS-8 is reduced and the loss of VLS-3 is increased, and
VLS・12 is controlled as having a predetermined loss, the high-level side system is set to low loss, the low-level side system is set to high loss, and the transmitting state or receiving state is set, and microphone 1-HA・2-
VLS・3-TA・4-HYB・5-RA・7-
The loop gain of the VLS/8-PA/9-speaker 10 is limited to a certain value or less so that no noise occurs.

FIG. 3 is a circuit diagram showing the main circuits of the VLS 12 and 13 and the control section ₁₁ in _FIG . )Q ₁ , the signal is amplified by a differential amplifier A ₁ having an input resistor R ₂ and a feedback resistor R ₃ , detected by a diode D ₁ , and smoothed by a capacitor C _1. , becomes the first DC voltage E _S having negative polarity.

In addition, the reception signal S _R is connected to the resistor _R4 and the FET.
After being amplified by a differential amplifier A ₂ with an input resistor R ₅ and a feedback resistor R ₆ through VLS 13 by Q ₂ , it is detected by a diode D ₂ in the opposite direction to the diode D ₁ . with capacitor
C ₂ and becomes a second DC voltage E _R with opposite polarity to the DC voltage E _S , and each voltage E _S ,
E _R is synthesized by resistors R ₇ and R ₈ connected in series with these, and each resistor R ₇ ,
Comparator CP as the composite voltage E from the common connection point of R ₈
is given to one input of

The comparator CP uses a differential amplifier with a feedback resistor _R9 , and since the composite voltage E is applied to the inverting input and the common potential as a reference voltage is applied to the non-inverting input, it operates as a zero-cross comparator. The polarity of the composite voltage E is DC voltage.
By determining E _S and E _R according to the higher voltage, the comparator C
The comparison output _EO has a polarity that is the inversion of the higher polarity of the DC voltages _ES and _ER .

Therefore, if the level of the sending signal S _T is higher than that of the receiving signal S _R , negative DC voltage E _S > positive DC voltage
_{E _ _ _ _ _ _} Therefore, depending on the polarity of comparison output E _O , VLS・3,
8 are controlled, and the transmitting state or the receiving state is respectively set.

However, in the transmitting state, when the transmitting signal to the RA/7 side via HYB/5 becomes high level, the polarity of the composite voltage E is reversed, and the polarity of the comparison output E _O is also reversed accordingly. and then switch to the listening state, which causes a transmission block in which transmission is interrupted.
In the receiving state, if the acoustic coupling level from the speaker 10 to the microphone 1 becomes high, the polarity of the composite voltage E and the comparison output E _O is reversed in the opposite direction to that described above, and the state is switched to the transmitting state, and the receiving state is interrupted. In order to generate a reception block, the control unit 11
Along with VLS 3 and 8, VLS 12 and 13 are also controlled at the same time, FET Q ₂ is turned off in the transmitting state, FET Q ₁ is turned off in the receiving state, and each resistor R ₄
Alternatively, a loss due to R ₁ is exhibited, and the level of the reception signal S _R or the transmission signal S _T related to the composite voltage E is reduced.

[Problem that the invention seeks to solve]

However, in the configuration shown in Figure 3, when the call is in the receiving state,
Loss insertion is done by VLS・12, and loss insertion is done by VLS・13 when in the transmitting state, and even if you start transmitting in the receiving state, the DC voltage E _S rises slowly, and similarly, when the transmitting state Even when a receiving signal arrives at , the rise in DC voltage E _R is slow, causing a delay in switching from receiving to transmitting or from transmitting to receiving, and the beginning of the transmitting signal sent to line 6 is delayed. Along with the disconnection, the beginning of the received voice emitted from the speaker 10 is cut off, causing problems in which the conversation becomes unnatural and the intelligibility deteriorates.

The present invention has the purpose of fundamentally solving the problems of the prior art, and provides a highly effective hands-free circuit with improved state switching speed.

[Means for solving problems]

In order to achieve the above-mentioned object, the present invention is constructed by the following means.

That is, each DC voltage is connected in series with the first DC voltage that detects the transmit signal and the second DC voltage that has the opposite polarity to the first DC voltage that detects the receive signal. A hands-free device that has a resistor and a comparator that compares the combined voltage from each resistor with a reference voltage and sends out a comparison output with a polarity depending on the higher voltage among the first and second DC voltages. In the circuit, a first bypass resistor sets the combination ratio of each resistor in a direction in which the first DC voltage is dominant, and a similar combination ratio is set in a direction in which the second DC voltage becomes dominant. Second
a bypass resistor; a first switching element that is inserted in series with the first bypass resistor and is turned on in response to a comparison output when the first DC voltage is a high voltage;
and a second switching element inserted in series with the second bypass resistor and turned on in response to a comparison output when the second DC voltage is a high voltage.

[Effect]

Therefore, in a transmitting state where the first DC voltage E _S is high, the first DC voltage E _S becomes dominant in terms of its contribution to the composite voltage E, eliminating the possibility of causing a transmitting block. In the receiving state where the second DC voltage E _R is high, the second DC voltage E _R becomes dominant due to the same degree of involvement, eliminating the possibility of receiving block, and VLS 12, 13
Since the amount of insertion loss can be reduced, each DC voltage E _S or E _R can quickly rise, and the state switching speed can be improved.

〔Example〕

The details of the present invention will be explained below with reference to the circuit diagram of FIG. 1 showing an embodiment.

This figure is similar to FIG. 3, except that resistors R ₁₁ to R ₁₆ and transistors Q ₁₁ and Q ₁₂ as switching elements are added. In Figure 1, resistors R ₁₁ and R ₁₂ are inserted in series to the common connection point of resistors R ₇ and R ₈ , respectively, and these common connection points are connected to the inverting input of comparator CP. and a first shunt resistor R ₁₃ is connected between the capacitor C ₁ and the connection point of the resistors R ₁₂ and R ₈ , and the capacitor C ₂ and the resistors R ₇ and R ₁₁ A second bypass resistor R ₁₄ is connected between the connection point and the connection point.

In addition, transistors Q 11 , R ₁₄ are connected to each resistor R ₁₃ , R ₁₄ as first and second switching elements.
The collector and emitter of _Q12 are inserted individually and in series, and their bases are connected to series resistors.
It is connected to the output of the comparator CP via R ₁₅ and R ₁₆ respectively.

Therefore, assuming the relationship R ₇ = R ₈ and R ₁₁ = R ₁₂ ,
When E _S > E _R due to S _T > S _R , the comparison output E _O becomes positive, and the NPN type transistor whose emitter is connected to the capacitor C ₁ and becomes negative polarity. By turning on Q ₁₁ and connecting resistor R ₁₃ in parallel with resistors R ₇ , R ₁₁ , and R ₁₂ , the combined ratio of E _S and E _R becomes a state where E _S is dominant. Therefore, a corresponding composite voltage E is generated, and even if the level of S _R rises to a certain extent, the positive polarity of the comparison output E _O does not reverse, and no transmit block occurs.

On the other hand, when S _T > S _R and E _S < E _R , the comparison output E _O becomes negative in accordance with this.
Since the PNP type transistor Q ₁₂ whose emitter is connected to the capacitor C ₂ is turned on and the resistor R ₁₄ is connected in parallel to the resistors R ₁₁ , R ₁₂ and R ₈ ,
The combination ratio of E _S and E _R due to these makes E _R dominant, and even if the level of S _T rises to a certain extent, the comparison output E _O maintains negative polarity and no reception block occurs.

In addition, for example, R ₇ = R ₈ = 62KΩ, R ₁₁ = R ₁₂ =
It should be about 10 to 20KΩ, R ₁₃ = R ₁₄ = 22KΩ, but resistors R ₁₁ and R ₁₂ are omitted, and resistors R ₇ and R ₁₃ are used.
The same applies to connecting R ₈ and R ₁₄ in parallel.

Also, the return paths of capacitors C ₁ and C ₂ are connected to the negative power supply, but this is because when a differential amplifier is used as the comparator CP, a power supply with both positive and negative polarities is used. , and can also be connected to a common potential depending on conditions.

Therefore, once the polarity of the comparison output E _O is determined, the composite voltage E shifts in the direction of maintaining this state, which reduces the insertion loss of VLS 12 and 13 compared to the conventional one. can be adjusted freely, and the resistor
Since the values of R ₁ and R ₂ can be set lower than those in FIG. 3, the rise in the DC voltage E _S in response to the start of transmission, or the rise in the DC voltage E _R in response to the arrival of the reception signal S _R increases quickly, the state switching speed from receiving to transmitting or from transmitting to receiving is improved, and the phenomenon of truncating the beginning of words in transmitted and received voices is reduced.

However, the configuration of VLS・12, 13 can be selected arbitrarily according to the conditions, and the polarity of the DC voltages E _S and _ER may be reversed, and other switching elements such as FETs can be used as the transistors Q ₁₁ and Q ₁₂ . The same applies to the use of these devices, and various modifications are possible, such as inserting an inverter or the like for these controls and turning them on and off in opposite directions.

〔Effect of the invention〕

As is clear from the above explanation, according to the present invention, the speed of state switching is improved by adding a simple circuit, and there is no fear of occurrence of a transmitting block or a receiving block, which is a remarkable effect as a hands-free circuit for various applications. is obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of a hands-free circuit, and FIG. 3 is a circuit diagram of a conventional example. R ₇ , R ₈ , R ₁₁ , R ₁₂ ...Resistor, R ₁₃ , R ₁₄ ...
Resistor (shunt resistor), CP...Comparator, Q ₁₁ , Q ₁₂
...transistor (switching element), S _T ...
Sending signal, S _R ...Receiving signal, E _S , E _R ... DC voltage, E ... Combined voltage, E _O ... Comparison output.

Claims (1)

[Claims] 1 connected individually in series with each of the DC voltages for synthesizing a first DC voltage that has detected a transmitting signal and a second DC voltage that has an opposite polarity to the first DC voltage that has detected a received signal; and a comparator that compares the combined voltage of each resistor with a reference voltage and sends out a comparison output with a polarity corresponding to a higher voltage among the respective DC voltages. a first bypass resistor that sets the combination ratio of each resistor in a direction in which the first DC voltage is dominant;
a second shunt resistor that is set in a direction in which the DC voltage of a first switching element that is turned on when the second DC voltage is high, and a second switching element that is inserted in series with the second bypass resistor and is turned on in response to the comparative output when the second DC voltage is a high voltage. A hands-free circuit characterized by comprising: