JPH02244372A - Load decentralized type multiprocessor interruption control system - Google Patents

Abstract

PURPOSE:To decentralize a load equally to respective processors by selecting one processor in a stop state if there is the processor in the stop state and initiating an interruption, and selecting one processor which initiate no interruption recently unless there is the processor in the stop state and initiating the interruption. CONSTITUTION:If an interruption factor is generated, an interruption controller 1 reads the states of respective processors 41, 42 - 4n through a processor state readout interface bus 2 and interrupts the processor 4i (i: 1, 2 - n) in the stop state through an interruption line 3 when there is the processor in the stop state. When there is no processor in the stop state, the processor 4j (j: 1, 2 - n) which causes no interruption recently is interrupted through the interruption line 3. The processor 4i or 4j which is informed by the interruption performs interruption processing. Consequently, the load is decentralized equally to the respective processors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control method in a load distributed multiprocessor system.

[Conventional technology]

Conventionally, in interrupt control methods for load-balanced multiprocessor systems, interrupts are generated only to a specific processor depending on the type of interrupt factor, or interrupts are generated to all processors so that each processor can receive an exclusive Processing rights are secured.

[Problem to be solved by the invention]

The interrupt control method in the conventional load-balanced multiprocessor system described above cannot uniformly distribute the load to each processor because it is not possible to select an arbitrary processor to execute interrupt processing when no interrupt factor occurs.

[Means to solve the problem]

The load-balanced multiprocessor interrupt control method of the present invention reads the status of each processor in the load-balanced multiprocessor when an interrupt factor occurs, and if any processor is in a stopped state, selects one of the stopped processors and generates an interrupt. and if there is no processor in a halted state, means is provided for selecting one processor that has not recently generated an interrupt and generating an interrupt.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Referring to FIG. 1, which shows one embodiment of the present invention, when an interrupt factor occurs, an interrupt control device 1 communicates with each processor 41 .
42 to 4n are read, and if there is a stopped processor, an interrupt is generated to the stopped processor 4i (i:l, 2 to n) via the interrupt line 3. On the other hand, if there is no processor in a stopped state, an interrupt is generated via the interrupt line 3 to a processor 4j (j: 1, 2 to n) that has not recently generated an interrupt. The processor 41 or 4j notified by the interrupt processes the interrupt.

〔Effect of the invention〕

As explained above, according to the present invention, when an interrupt factor occurs, the status of each processor is read, and if there is a stopped processor, one of the stopped processors is selected to generate an interrupt, and the stopped processor is If not, by selecting one processor that has not recently generated an interrupt and generating an interrupt, the load can be evenly distributed to each processor.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Interrupt control device, 2... Processor status read interface bus, 3... Interrupt line, 41°4
2-4n...processor.

Claims (1)

[Claims] When an interrupt factor occurs, the status of each processor in the load-balanced multiprocessor is read, and if there is a stopped processor, one of the stopped processors is selected to generate an interrupt, and if there is no stopped processor, the most recent interrupt is generated. 1. A load-distributed multiprocessor interrupt control system comprising means for selecting one processor that is not generating an interrupt and generating an interrupt.