JPH0318222B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an array processor device that performs matrix and vector operations on large-capacity data such as image data.

[Technical background of the invention and its problems]

As is well known, array processor devices are used in processes such as image processing, in which repetitive calculations such as matrix and vector operations are performed at high speed. Further, in its general usage form, as shown in FIG. 1, an array processor device 12 and other known devices 13 are connected to a general-purpose computer (for example, a minicomputer) 11, 13 is controlled by the general-purpose computer 11 and inputs and outputs necessary data.

In order to perform high-speed processing in the configuration of this type of array processor device, the signal processors (unit processors forming the array) often have a pipeline structure or a parallel structure. However, even with this structure, it is difficult to make full use of the functions of the array processor when it is used only for limited processing. In other words, if only a part of the pipeline structure or a part of the processors in the parallel structure can perform sufficient processing, there is plenty of room for processing, but there is a lot of waste. However, if dedicated hardware is developed for a certain amount of fixed processing, it is possible to obtain a device with sufficient performance, but it becomes difficult to apply the device to other processing. However, it has the disadvantage that it lacks versatility.

[Purpose of the invention]

This invention was made based on the above circumstances, and its purpose is to make it possible to arbitrarily set the number of pipeline stages and degree of parallelism by switching a switch, and to achieve an excellent result with a minimal configuration. The present invention aims to provide an array processor device that can achieve high speed and versatility.

[Summary of the invention]

This invention provides a processor group in which a plurality of signal processors are connected in parallel between input and output buses, a storage unit to which the processor group is connected via an output bus, and a state in which the input buses of these processor groups are commonly connected. and a switch control means for switching to a state in which the output bus and input bus of adjacent processor groups are connected.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows an array processor device, which, like FIG. 1, is comprehensively controlled by a general-purpose computer (for example, a minicomputer or a microcomputer). Here, 21 ₁ , 21 ₂ to 21n are processor groups, respectively. This processor group 21 ₁ , 2
₁₂ to 21n are a plurality of signal processors _P11 , _P21 to _Pm1 , _P12 , connected between input buses _I1 , _I2 to In and output buses _O1 , _O2 to On, respectively.
It is composed of P ₂₂ ~Pm ₂ ...P ₁ nP ₂ nPmn.
Each processor group 21 ₁ to 21n having such a configuration
One ends of the output buses O ₁ to On are connected together and connected to the capacity memory 23 via the input/output control section 22 . This large-capacity memory 23 is constituted by, for example, a semiconductor memory or a magnetic disk device. In the case of a semiconductor memory, it is built into an array processor device, and in the case of a magnetic disk device, data is stored in the same way as the well-known device 13 shown in FIG. connected to the bus. Further, an input bus of the processor group 21 ₂ to 21n
Movable contacts S ₂₁ and S ₃₁ to Sn ₁ forming switches S ₂ and S ₃ to Sn are provided at I ₂ to In, respectively. Constant fixed contacts _S22 , _S32 ~ _Sn2 of this switch _S2 , _S3 ~Sn
are processor groups 21 ₁ , 21 ₂ to 21 _o-1, respectively.
(not shown) is connected to the other end of the output bus O ₁ , O ₂ ~ _{O o-1} , and the other fixed connection of the switch S ₂ , S ₃ ~ Sn
S ₂₃ , S ₃₃ to Sn ₃ are each connected to the input bus I ₁ of the processor group 21 ₁ . This input bus I ₁ is connected to a mass memory 23 via the input/output control section 22 .

It should be noted that the signal processors P ₁₁ to Pmn all have the same configuration, and are composed of, for example, one VLSI or a plurality of ICs. FIG. 3 shows an example of a signal processor, and 31 is an input/output interface connected to an input/output bus.
Further, 32 is a program memory, and a data memory 33 and a coefficient memory 34 are accessed by the program stored in this memory 32, and predetermined calculations are performed via a processing memory 35, an adder 36, and an integrator 37. will be held. Output of this calculation result or other signal processor or large capacity memory 23
Data input/output is performed via the input/output interface 31.

In the above configuration, if the movable contact pieces S ₂₁ -Sn ₁ of the switches S ₁ , S ₂ -Sn are all connected to the fixed contacts S ₂₂ -Sn ₂ as shown in FIG. Can be processed.

To explain the operation when performing pipeline calculation in the state shown in FIG.
The original data is input to the processor group ₂₁₁ via. This data is input to each signal processor in the processor group ₂₁₁ in the order of _P11 , _P21 ..., _Pn1 . Processing is started at the same time as the data is input to each signal processor. Processing ends in the order of signal processors P ₁₁ , P ₂₁ ..., Pn ₁ , but as soon as it ends, data is transferred to output bus O ₁ in the order of P ₁₁ , P ₂₁ ..., Pn ₁ under control from the general-purpose computer. is output. This data is processed by processor group 2.
1 ₂ input bus I ₂ to the processor group 21 ₂
Input to each signal processor. Thereafter, the same operations as in the processor group ₂₁₁ are repeated. Finally, the output of the processor group is transferred to the large capacity memory via the input/output control section 22. In addition, the movable contact piece
When all of S ₂₁ to _{Sn 1} are connected to fixed contacts S ₂₃ to Sn ₃ , parallel processing can be performed by all signal processors from P ₁₁ to Pmn. At this time, the outputs of each stage are connected to a common bus, but data collisions are avoided by a general-purpose computer that comprehensively controls the array processor device. That is, a well-known method is used in which a general-purpose computer monitors the processing status of the signal processors at each stage and the bus usage status, and grants output permission to each stage of the signal processor. The switches S ₂ to Sn can be set manually or by software. For example, when performing fixed processing, the switch is fixed at a predetermined state, and when performing processing that changes in time series, the switch can be switched programmably by the general-purpose computer to enable high-speed calculation. .

According to the above configuration, it is possible to arbitrarily set the number of pipeline stages or the degree of parallelism of the signal processor by switching the switches S ₂ to Sn. Therefore, it is possible to configure the array processor device as necessary and sufficient according to the processing purpose and amount of data, so that superior high speed and versatility can be achieved compared to the conventional method.

Furthermore, since one array processor device can be applied to various processing purposes, there is no need to develop dedicated devices depending on the processing purpose, etc., which is excellent in terms of economic efficiency.

Furthermore, since the signal processors are arranged in a matrix, the structure can be easily changed by simply switching the switches S ₂ -Sn, and this control is also easy.

Further, when processing is performed in a certain structure, a signal processor for backup can be connected as necessary by operating the switches S ₂ -Sn, so a highly reliable design is possible.

〔Effect of the invention〕

As detailed above, according to the present invention, the number of pipeline stages and degree of parallelism can be arbitrarily set by switching the switch.
It is possible to provide an array processor device that can obtain excellent high speed and versatility with a minimum necessary configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing how an array processor is used, FIG. 2 is a block diagram showing an embodiment of the array processor according to the present invention, and FIG. 3 is a block diagram showing an example of a signal processor. It is. 21 ₁ , 21 ₂ to 21n...processor group, P ₁₁
~Pmn...Signal processor, _I1 ~In...Input bus, _O1 ~On...Output bus, S2 _~ Sn...Switch, 23...Large capacity memory.

Claims (1)

[Claims] 1. An input bus and an output bus that are connected to a large-capacity memory via an input/output control unit, a processor group in which a plurality of signal processors are connected between these input/output buses, and a processor group that is connected to a large capacity memory via an input/output control unit. A plurality of other processor groups connected to each other, a switch control means for switching between a state in which input buses of these processor groups are commonly connected and a state in which output buses and input buses of adjacent processor groups are connected, These are characterized in that they are controlled by a general-purpose computer that monitors the processing status and usage status of the signal processors at each stage of the array processor device and gives output permission to each stage signal processor. array processor device.