JPH022443A - Transmitting/receiving two-way communication system using dma control system - Google Patents

Abstract

PURPOSE:To prevent transmission from being canceled even when transmission and receiving are executed in the same timing by allowing a DMA control part to continuously hold its transmitting state during the left period of transmission data even after the end of data reception by a CPU. CONSTITUTION:At the time of receiving a reception request, the CPU 1 executes the processing of receiving DMA and then checks a transmitting data counter. When the contents of the counter are '0', there are no data being practically transmitted, so that the reception of a communication controller 3 is set up to a DMA mode and bit 1 (b1) of a command register in a DMA control part 2 is set up to '1'. When the contents of the counter are not '0', the reception of the controller 3 is set up to the DMA mode and both the bits 2, 1 (b2, b1) of the command register in the DMA control part 2 are set up to '1'. Thereby, a DMA control part 2 executes DMA control until the contents of the transmitting data counter are set up to '0', i.e. until all the data are practically transmitted.

Description

[Detailed Description of the Invention] [Summary] Regarding a transmission/reception bidirectional communication system using a DMA control system, the purpose of this invention is to prevent transmission from being aborted even when transmission and reception occur at the same timing. The U, DMA ff4 control unit, asynchronous bidirectional communication controller, and memory are connected, and the DMA control unit is configured to perform asynchronous bidirectional communication under the control of the DMA control unit by setting operating conditions from the CPU. DMA configured to directly send and receive data between memory and the outside via a controller
In a transmission/reception bidirectional communication system using a control method, CP
U is configured to cause the DMA control unit to continue to maintain the transmission state while transmission data remains after data reception is completed.

[Industrial application field]

The present invention relates to a transmission/reception bidirectional communication system using a DMA (direct memory access) control system, and in particular, to a transmission/reception bidirectional communication system that prevents transmission from being substantially interrupted even if transmission and reception occur at the same timing. Regarding communication methods.

The transmitting/receiving bidirectional communication method using the DMA control method of the present invention is oMa! Various two-way communication methods using the IJm method and in which transmission and reception are performed within the same timing,
For example, it can be used in TDMA (time division multiple access) communication systems in satellite communications.

[Conventional technology]

The DMA control method is widely used in computer systems to read and write data at high speed and to reduce the burden on the CPU. In other words, the CPU sets the conditions for reading or writing data to the control unit. Data can be read or written directly by simply setting
DMA connected via bus without going through Pu
This is done directly between the M control and memory.

It is known that data is transmitted and received from the outside using such a DMA control method. For this purpose, it is known as USART, etc., and is commercially available as an LSI chip.
An asynchronous two-way communication controller is provided.

An example of a device that performs such data communication is a system that sends and receives data between a computer and a floppy disk. However, in such a system, when data is transmitted from one side, the data is not received, that is, the transmission and reception are not performed at the same timing, so the problem described later in the present invention does not occur. Therefore, it is not of interest to the present invention.

On the other hand, in the TDMA satellite communication system shown in FIG. 5, transmission and reception may occur within the same timing in both the base station and the slave station. A demand assignment control device connected to the reference station centrally controls the assignment of time-division time slots on the satellite link. Therefore, the satellite line assignment circuit in each slave station and the demand assignment control device are transparently connected via the line. Since these line communications govern time slot allocation, particularly high reliability is required, and the High Level Data Link Control Procedure (HDLC) protocol is used. That is, according to the HDLC protocol, unlike the basic data transmission control procedure, highly efficient data transmission is possible without any coding restrictions. That is, the HDLC in the demand assignment control device has a function of transparently and efficiently transmitting data to slave stations.

The same applies to the HDLC in the satellite line assignment circuit.

For this reason, for example, when considering a demand assignment control device, it must be capable of not only transmitting data but also receiving data from slave stations. Also, data reception occurs during data transmission. USART is used to control such data transmission and reception.

FIG. 6 shows a configuration diagram of a conventional communication system using a DMA control unit 2a and a USART 3a. In the same figure,
DMA control section 2a via CPU bus 6a.

IJSART 3a and memory 4a are connected to CPII f a. Also USART 3 a and CPUra
An interrupt control section 5a is connected between the two.

FIG. 7 shows the registers in the DMAlli section 2a, that is,
Command (COMMAND register, transmit transfer by)
(TXBYTI counter, receive transfer byte (RXB)
YTE) counter, transmission transfer start address (TXTOP
) register, indicates the receive transfer start address (RXTOP) register.

The COMMAND register is 8 bits, and the other registers are 16 bits. When set, pins) 2.1 (b2.bl) of the COMMAND register perform transmit DMA control and receive D? Indicates that lA control is performed.

CPU r is D? By setting appropriate parameters in the upper register of the lA control unit 2a, the USART 3a can be connected between the memory 4a and the outside without going through the CPUra.
Transmission data (TX data) or reception data (RX data) is exchanged via the DMA control unit 2a.

FIG. 8 shows an operation flowchart for controlling the CPURA DMA control unit 2a.

In general, since it is not known when reception will occur,
MAfH control must always be enabled, so in step 3003 of FIG.
Bit 1 (bl) of the OMMAND register is set. Even if there is a transmission and no reception, step S0
At 07, bit 2.1 of the COMMAND register
(b2.bl) is set. When the transmission is finished,
Bit 2 (b2) of the COMMAND register is reset.

[Problem to be solved by the invention]

When transmitting 6 bytes of transmission data under DMA control as shown in FIG. As soon as the data to be sent is set, it is transferred from Kano to the CPU. However, the actual data transmission is shown in Figure 9 (C
), this is done even after bus control is transferred to the CPU.

Here, as shown in FIG. 9, DMA control of the received data occurs while the data is actually being transmitted, and the amount of received data is small and the data is received before the data transmission has finished. When the data DMA control is completed, in the process shown in FIG. 8, bit 2 of the COMMAND register is
We have encountered a problem where it is unclear whether (b2) should be set to 0" or "1".

If b2=0, the DMA control unit 2a will not perform any further transmission processing, and the subsequent data transmission will be aborted. On the other hand, if b2=1, even if the transmission has already been completed, the DMAffd control unit 2a will be forced to perform a non-existent transmission.

In other words, if control of the bus for transmission is once returned to the CPU side, and reception occurs and the processing is completed before the actual transmission ends, how should the DMA control of transmission be performed?
This has become a problem. This is based on the difference in timing between bus control and actual DMA control.

[Means for Solving the Problems and Operations] FIG. 1 shows a principle block diagram of a transmitting/receiving two-way communication system using the DMA control system of the present invention.

In the same figure, the communication method is that the CPU
T, D? The IAII control unit 2, the asynchronous bidirectional communication controller 3, and the memory 4 are connected, and the DMA control unit receives operating conditions from the CPU, so that the DMA control unit can communicate via the asynchronous bidirectional controller under the control of the DMA control unit. The device is configured so that data can be directly transmitted and received between the memory and the outside. Communication controller 3 and CPU
1 and can be connected to the interrupt control unit 5.

The circuit configuration shown in FIG. 1 is a generalized version of the circuit configuration shown in FIG. However, the control processing of CPU 1 is
As shown in the figure, they are different.

When there is a reception request, the CPU 1 executes reception DMA processing and then checks the transmission data counter. If the transmission data counter is 0, there is no data actually being transmitted, so the reception by the communication controller 3 is
Set to MA mode, DMA system? 11 Set bit 1 (bl) of the ND register to COM- of part 2 to 1. If the transmission data counter is not O, the communication controller 3
The reception of the DMA controller 2 is set to DMA mode, and
Bit 2.1 (b2.bl) of the MMAND register
Set both to 1.

As a result, the DMA control unit 2 sets the transmission data counter to 0.
DMA@?, i.e. until all transmitted data is actually transmitted. Do step 11.

[Embodiment] FIG. 3 shows a configuration diagram of a transmitting/receiving bidirectional communication system using a DMA control system according to an embodiment of the present invention. As mentioned above, this embodiment exemplifies the case where it is applied to the TDMA satellite communication system shown in FIG.

The configuration of the communication system shown in FIG. 3 is similar to the communication system shown in FIG. 6, but the processing of the CPU l a is different as shown in FIG. 4. Note that the registers in the DMA control section 2a shown in FIG. 8 are the same as in FIG.

Hereinafter, with reference to the flowchart in Figure 4, the CP in Figure 3 will be explained.
The operation of U1 will now be described.

Soup 001-003 3001-3003 Theft the communication transfer start address (TXTOP) register and reception transfer start address (RXTOP) register to 0 (
S 001), then send USART 3 a,
Set reception to DMA mode (SOO2), that is,
Although the USART 3a can operate under the control of the CPU 1a or under DMA control, both transmission and reception are set to DMA mode. Additionally, set the receive transfer byte (RXBYTH) counter to maximum! Set to 0 in the frame Next, bit 1 (bl) indicating reception DMA enablement of the command (COMMAND) register is set (5003), thereby enabling reception under DMA control.

In the case of sending processing without receiving processing (S 004, S
005), transmission transfer pie) (TXBYTE) register indicates the number of data to be transmitted, for example, 6 as shown in Figure 5(e).
Set byte 0 then DMAIIJ? Set bit 2 (b2) of the COMMAND register so that data transmission occurs under il, and receive D? Bit 1 (bl) of the COMMAND register to disable IA
(3003).

As a result, transmit DMA processing is performed (3008
).

As shown in FIG. 5(b), when the transmission of 6 bytes is completed, as shown in FIG. 5(a), the CPU 1 a
transfers bus control from DMA to CPU. This results in c
pυ cancels the inhibition of reception processing (SOO9).

As a result, there is a possibility that reception DMA will occur as shown in FIG. 5(b).

When there is reception processing (SOO4), the reception DMA processing is executed (SOII), and then the TxBYTE counter is set to 0.
Check whether it is true (3021). As shown in FIG. 5(e), if the TXBYTI! counter is not 0 when the receive DMA process ends at the timing shown in FIG. Therefore, set the RXTOP register to 0, set USART 3 a to receive DMA mode (5O22), and set both bits 2 and l (b2.bl) of the COMMAND register (302).
3).

That is, b2 of the C0M1'1AND register continues to be set.

If TXBYTIE-0, return to step 001,
Shift to initial reception settings.

The state of bit 2.1 of the above C0M1'1AND register is shown in FIG. 5(f) @.

As described above, unless the [1, MA processing of the transmitted data is actually continuing (Fig. 5 (c)) and the TXBYTE counter is not 0 (Fig. 5 (e)), the received Even if there is an opening and it ends first, it will not be interrupted.

〔Effect of the invention〕

As described above, according to the present invention, data transmission is performed under DMA control, and control of the bus is controlled by cpυ
If the data transmission continues at the time when the reception DMA occurs and the reception DMA ends first, the data transmission is performed to the end without interruption.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of a transmitting/receiving bidirectional communication method using the DMA control method of the present invention, Fig. 2 is a flowchart explaining the operation of the borrowing method shown in Fig. 1, and Fig. 3 is a communication method according to an embodiment of the present invention. 4 is an operation flowchart of the CPU in FIG. 3, and FIG. 5(a) to
(6) is an operation timing diagram of the communication system shown in FIG. 3, and FIG. 6 is a TO? to which the present invention is applied. I^Satellite communication system Figure 7 is a configuration diagram of a conventional communication system, Figure 8 is a diagram of the internal register configuration of the controller in Figure 7, Figure 9 is a flowchart explaining the operation of the CPU in Figure 7, 1O (a) to (d) are operation timing diagrams of the communication system of FIG. 7. (Explanation of symbols) 1.1a...CPU, 2...Open^ control unit, 3...Asynchronous bidirectional communication controller, 4...Memory, 5...Interrupt control unit, 6. ··bus.

Claims (1)

[Claims] 1. The CPU (1) and the DMA control unit (
2) The asynchronous bidirectional communication controller (3) and the memory (4) are connected, and the DMA control section is configured with operating conditions from the CPU, so that the asynchronous bidirectional communication controller operates under the control of the DMA control section. In a two-way communication system using a DMA control system, in which data is directly transmitted and received between the memory and the outside via a 1. A two-way transmission/reception communication system using a DMA control system, characterized in that the DMA control unit (2) is configured to continuously maintain a transmission state during a period of time.