JPH0224633U

JPH0224633U -

Info

Publication number: JPH0224633U
Application number: JP10212588U
Authority: JP
Priority date: 1988-08-01
Filing date: 1988-08-01
Publication date: 1990-02-19
Anticipated expiration: 2003-08-01
Also published as: JPH0625058Y2

Description

[Brief explanation of the drawing]

第１図はこの考案の実施例を示すブロツク図、
第２図は第１図の動作を説明するためのタイムチ
ヤート、第３図はこの考案の他の実施例を示すブ
ロツク図、第４図は第３図の動作を説明するため
のタイムチヤート、第５図は従来の波形ホーマツ
タを示すブロツク図、第６図はその動作を説明す
るためのタイムチヤートである。 Figure 1 is a block diagram showing an embodiment of this invention.
2 is a time chart for explaining the operation of FIG. 1, FIG. 3 is a block diagram showing another embodiment of this invention, and FIG. 4 is a time chart for explaining the operation of FIG. 3. FIG. 5 is a block diagram showing a conventional waveform generator, and FIG. 6 is a time chart for explaining its operation.

Claims

[Claims for Utility Model Registration] (1) A first OR gate to which a plurality of setting timing clocks are applied; a first delay circuit to which the output of the first OR gate is supplied and whose delay amount is _t0 ; 1st A to which the output of the 1OR gate is supplied
an ND gate, a first variable delay circuit to which the output of the first AND gate is supplied and whose delay amount is _t0 + _t1 , a second OR gate to which a plurality of reset timing clocks are supplied, and an output of the second OR gate. a second delay circuit which is supplied with a delay amount of _t0 , and a second delay circuit which is supplied with the output of the second OR gate.
an ND gate, a second variable delay circuit which is supplied with the output of its second AND gate and has a delay amount of t ₀ -t ₂ , and is set by the output of the first delay circuit and the output of the second variable delay circuit; A waveform formatter comprising: a flip-flop reset by the output of the second delay circuit and the output of the first variable delay circuit. (2) First, second, and third variable delay circuits to which the timing clocks for the first, second, and third sets are supplied, respectively, and the outputs of these first, second, and third variable delay circuits are supplied. a fourth, fifth, and sixth variable delay circuit to which the first, second, and third reset timing clocks are supplied, respectively; and these fourth, fifth, and sixth variable delay circuits. a second OR gate to which an output is supplied; and a first OR gate to which the timing clocks for the first, second, and third sets are respectively supplied and whose outputs are supplied to the fourth, fifth, and sixth variable delay circuits, respectively. , second and third AND gates, and a fourth circuit, which is supplied with the first, second and third reset timing clocks, respectively, and supplies its output to the first, second and third variable delay circuits, respectively.
is set by the outputs of the fifth and sixth AND gates and the first OR gate,
A waveform generator comprising: a flip-flop reset by the output of the second OR gate;